Patents by Inventor John D. Porter
John D. Porter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240125851Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.Type: ApplicationFiled: October 18, 2022Publication date: April 18, 2024Applicant: Micron Technology, Inc.Inventors: Kenneth M. Curewitz, Jaime Cummins, John D. Porter, Bryce D. Cook, Jeffrey P. Wright
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Patent number: 11959422Abstract: A brush seal system includes a component including a first mating surface. The brush seal system further includes a brush seal including a brush seal backing plate, a retaining ring, and a plurality of bristles retained between the brush seal backing plate and the retaining ring. The brush seal backing plate includes a second mating surface mounted to the first mating surface. The brush seal system further includes at least one cooling channel extending from an exterior side of the component to an interior side of the component so as to bypass the brush seal.Type: GrantFiled: April 3, 2023Date of Patent: April 16, 2024Assignee: RTX CORPORATIONInventors: Caroline Karanian, Steven D. Porter, John T. Ols
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Patent number: 11955162Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.Type: GrantFiled: May 5, 2023Date of Patent: April 9, 2024Inventors: Dean D. Gans, John D. Porter
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Publication number: 20240071431Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense components. Moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. For example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. Such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Si Hong Kim, John D. Porter
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Publication number: 20240071456Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Si Hong Kim, John D. Porter
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Publication number: 20240004751Abstract: An on-die controller can provide an error correction capability for data stored in an array of memory cells located on the same die as the on-die controller. The error correction capability provided by the on-die controller eliminates a need to transfer error correction code (ECC) data to an external controller that may have provided the error correction capability in lieu of the on-die controller, which can provide more channel bandwidth for other types of non-user data for further strengthening data reliability, security, integrity of the memory system.Type: ApplicationFiled: June 29, 2023Publication date: January 4, 2024Inventors: Marco Sforzin, John D. Porter
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Publication number: 20230420032Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.Type: ApplicationFiled: May 5, 2023Publication date: December 28, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Dean D. Gans, John D. Porter
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Patent number: 11804281Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.Type: GrantFiled: October 12, 2021Date of Patent: October 31, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Donald M. Morgan, Alan J. Wilson, Bryan D. Kerstetter, John D. Porter
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Patent number: 11682447Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.Type: GrantFiled: January 28, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, John D. Porter
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Patent number: 11646065Abstract: An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.Type: GrantFiled: July 2, 2021Date of Patent: May 9, 2023Assignee: Micron Technology, Inc.Inventor: John D. Porter
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Publication number: 20230116534Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.Type: ApplicationFiled: October 12, 2021Publication date: April 13, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Donald M. Morgan, Alan J. Wilson, Bryan D. Kerstetter, John D. Porter
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Patent number: 11594272Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.Type: GrantFiled: August 23, 2021Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Huy T. Vo, Adam S. El-Mansouri, Suryanarayana B. Tatapudi, John D. Porter
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Patent number: 11335393Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.Type: GrantFiled: February 10, 2021Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventors: Yoshiro Riho, Yoshinori Matsui, Kiyohiro Furutani, Takahiko Fukiage, Ki-Jun Nam, John D. Porter
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Patent number: 11282560Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.Type: GrantFiled: March 22, 2021Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Victor Wong, Sihong Kim, Hiroshi Akamatsu, Daniele Vimercati, John D. Porter
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Patent number: 11276455Abstract: A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes a sense amplifier and associated circuitry configured to detect a first threshold representative of a first external voltage ramping down during a power off of the memory device, and one or more switches triggered via the sense amplifier and associated circuitry to provide for a power off sequence for the memory bank based on using a second external voltage ramping down during the power off of the memory device.Type: GrantFiled: October 28, 2020Date of Patent: March 15, 2022Assignee: Micron Technology, Inc.Inventors: Takamasa Suzuki, Yasushi Matsubara, John D. Porter, Ki-Jun Nam
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Patent number: 11262941Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.Type: GrantFiled: May 15, 2019Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Kang-Yong Kim, Hyun Yoo Lee, John D. Porter
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Publication number: 20210383856Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Inventors: Huy T. Vo, Adam S. El-Mansouri, Suryanarayana B. Tatapudi, John D. Porter
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Publication number: 20210335399Abstract: An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Inventor: John D. Porter
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Publication number: 20210304806Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.Type: ApplicationFiled: March 22, 2021Publication date: September 30, 2021Inventors: Victor Wong, Sihong Kim, Hiroshi Akamatsu, Daniele Vimercati, John D. Porter
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Patent number: 11127449Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.Type: GrantFiled: April 25, 2018Date of Patent: September 21, 2021Assignee: Micron Technology, Inc.Inventors: Huy T. Vo, Adam S. El-Mansouri, Suryanarayana B. Tatapudi, John D. Porter