Abstract: A data processing system includes a plurality of switch points interconnected by a write data network and a write request network. Each switch point includes write request switch circuitry having write request ingress ports and write request egress ports coupled to the write request network and arbitration circuitry configured to grant a write request received at one of the write request ingress ports access to one of the write request egress ports. Each switch point also includes write data switch circuitry having write data ingress ports and write data egress ports coupled to the write data network. In response to the write request arbitration circuitry granting the write request, allowing write data from the write data ingress port corresponding to the one of the write request ingress ports to be provided at the write data egress port which corresponds to the one of the write request egress ports.

Abstract: A data processing system includes a network of interconnected switch points having a plurality of edge switch points located at an edge of the network; a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers; a plurality of target controllers; and a crossbar switch coupled between the plurality of network interface controllers and the plurality of target controllers. The crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target controllers.

Abstract: A data processing system includes a plurality of switch points interconnected by a write data network and a write request network. Each switch point includes write request switch circuitry having write request ingress ports and write request egress ports coupled to the write request network and arbitration circuitry configured to grant a write request received at one of the write request ingress ports access to one of the write request egress ports. Each switch point also includes write data switch circuitry having write data ingress ports and write data egress ports coupled to the write data network. In response to the write request arbitration circuitry granting the write request, allowing write data from the write data ingress port corresponding to the one of the write request ingress ports to be provided at the write data egress port which corresponds to the one of the write request egress ports.

Abstract: Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

Abstract: A plurality of processing units are interconnected by a coherency network in accordance with a directed spanning tree. Each processing unit that is a leaf of the directed spanning tree includes processing circuitry to provide a coherency response in response to a snoop request. Each processing unit which is not a root or leaf of the directed spanning tree includes switch point circuitry having one or more ingress ports coupled to neighboring processing units in accordance with the directed spanning tree. The switch point circuitry includes a coherency tracking table configured to store a combined coherency response in response to a particular snoop request based on one or more coherency responses received at the one or more ingress ports from the neighboring processing units.

Abstract: A network having a plurality of switch points, each switch point having both a main multi-stage pipeline and a look-ahead pipeline between input ports and output ports of the plurality of switch points is described. The look-ahead pipeline has fewer pipeline stages than the main multi-stage pipeline. Look-ahead information and corresponding packet are received at an input port. A first stage look-ahead request is generated from the look-ahead information. A second stage look-ahead request is generated in response to the first stage look-ahead request being not granted. And in response to the second stage look-ahead request being granted, transmitting a packet through the switch point using the look-ahead pipeline.

Abstract: Piggy-back snoops are used for non-coherent memory transactions in distributed processing systems. Coherent and non-coherent memory transactions are received from a plurality of processing cores within a distributed processing system. Non-coherent snoop information for the non-coherent memory transactions is combined with coherent snoop information for the coherent memory transactions to form expanded snoop messages. The expanded snoop messages are then output to a snoop bus interconnect during snoop cycles for the distributed processing system. As such, when the processing cores monitor the snoop bus interconnect, the processing cores receive the non-coherent snoop information along with coherent snoop information within the same snoop cycle. While this piggy-backing of non-coherent snoop information with coherent snoop information uses an expanded snoop bus interconnect, usage of the coherent snoop bandwidth is significantly reduced thereby improving overall performance of the distributed processing system.

Abstract: A network having a plurality of switch points, each switch point having both a main multi-stage pipeline and a look-ahead pipeline between input ports and output ports of the plurality of switch points is described. The look-ahead pipeline has fewer pipeline stages than the main multi-stage pipeline. Look-ahead information and corresponding packet are received at an input port. A first stage look-ahead request is generated from the look-ahead information. A second stage look-ahead request is generated in response to the first stage look-ahead request being not granted. And in response to the second stage look-ahead request being granted, transmitting a packet through the switch point using the look-ahead pipeline.

Abstract: A plurality of processing units are interconnected by a coherency network in accordance with a directed spanning tree. Each processing unit that is a leaf of the directed spanning tree includes processing circuitry to provide a coherency response in response to a snoop request. Each processing unit which is not a root or leaf of the directed spanning tree includes switch point circuitry having one or more ingress ports coupled to neighboring processing units in accordance with the directed spanning tree. The switch point circuitry includes a coherency tracking table configured to store a combined coherency response in response to a particular snoop request based on one or more coherency responses received at the one or more ingress ports from the neighboring processing units.

Abstract: A data processing system includes a network of interconnected switch points having a plurality of edge switch points located at an edge of the network; a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers; a plurality of target controllers; and a crossbar switch coupled between the plurality of network interface controllers and the plurality of target controllers. The crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target controllers.

Abstract: Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

Abstract: Piggy-back snoops are used for non-coherent memory transactions in distributed processing systems. Coherent and non-coherent memory transactions are received from a plurality of processing cores within a distributed processing system. Non-coherent snoop information for the non-coherent memory transactions is combined with coherent snoop information for the coherent memory transactions to form expanded snoop messages. The expanded snoop messages are then output to a snoop bus interconnect during snoop cycles for the distributed processing system. As such, when the processing cores monitor the snoop bus interconnect, the processing cores receive the non-coherent snoop information along with coherent snoop information within the same snoop cycle. While this piggy-backing of non-coherent snoop information with coherent snoop information uses an expanded snoop bus interconnect, usage of the coherent snoop bandwidth is significantly reduced thereby improving overall performance of the distributed processing system.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A wheel work chair has all the attributes and style of an office chair but is equipped with wheelchair-type supporting wheels The chair is height adjustable with the upper portion of the chair moving relative to the lower portion of the chair. Wheels connected to the upper portion of the chair move with the chair seat as the height of the chair is adjusted. Wheels connected to the lower portion of the chair remain on the ground as the height of the chair is adjusted. A static surface is provided on the arm of a height adjustable chair to support the weight of a user while that chair is being raised.

Abstract: A height adjustable structure comprises a base, a height adjustment column disposed above the base and supported thereon, and a table top or chair seat support disposed above the height adjustment column. Alternatively the height adjustable structure comprises two or more base sections, a height adjustment column disposed above each base section and supported thereon, and a table top or chair seat support disposed above the height adjustment columns. Each height adjustment column comprises a telescoping spring height adjustment lifting mechanism. The telescoping spring height adjustment lifting mechanism is typically a gas spring. Actuation mechanisms which actuate or unlock each lockable telescoping spring height adjustment lifting mechanism are used to allow the user to easily make height adjustments. The actuation mechanisms may extend above the table top. Connecting bars may be used to connect more than one actuation mechanism.

Abstract: A height adjustable chair has an upper portion that moves relative to a lower portion. Push-off arm rests are provided so that a person need not leave the chair to adjust the seat height upwardly. A seated person can transfer their body weight to the push-off arm rests supported directly by the stationary lower portion while the seat is being adjusted upwardly.

Abstract: Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

Abstract: A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.