Abstract: A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit.

Abstract: A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.

Abstract: An ergonomic footrest comprises a chair attachment bracket for attachment to the underside of a work chair seat, a footrest actuating mechanism supported by the chair attachment bracket for rotational movement in relation to the chair attachment bracket, and a footrest mechanism including a footrest brace and at least one footrest support arm. The footrest support arms each have a first and second end. The first end of at least one support arm is attached to the footrest brace. The second end of at least one support arm is attached to the footrest actuating mechanism. The support arms moveably suspend the footrest brace in relation to the chair attachment bracket. Rotational movement of the footrest actuating mechanism causes the footrest brace to move in relation to the chair attachment bracket. Rotational movement of the footrest actuating mechanism is typically manually performed through the rotation of arm rests or hand grips which are integrated into the actuating mechanism.

Abstract: A height adjustable pedestal comprises a base, a height adjustment column disposed above the base and supported thereon, and a table top or chair seat support disposed above the height adjustment column. The height adjustment column comprises at least two spring actuated telescoping height adjustment mechanisms. The height adjustment column typically additionally includes at least one stand tube each having a first and a second end. The first end includes an opening or hole through which a telescoping height adjustment mechanism passes. The second end of each stand tube is proximate to the base. At least one support, disposed vertically above or below the base of the pedestal, for securing the stand tubes together, may also be included. Telescoping height adjustment mechanisms used in the pedestal are typically gas springs. Supports for securing the stand tubes together may comprise a platform. Such platforms include attachment means to attach the platform to the base.

Abstract: A non-swiveling height adjustable work chair comprises a seat, a base, and a non-swiveling height adjustment column disposed intermediate the base and the seat. The height adjustment column comprises at least two telescoping height adjustment mechanisms, wherein the telescoping height adjustment mechanisms secure the seat against rotation in relation to the chair base. The chair additionally comprises a lever to actuate the height adjustment mechanisms. The height adjustment column may typically comprise a single stand tube having a first and a second end, wherein the first end is attached to the chair base and extends vertically therefrom, and the second end includes at least two holes through which the telescoping height adjustment mechanisms pass.

Abstract: The foot rest mechanism of the present invention comprises chair attachment means for attachment to the underside of a work chair seat, a foot rest actuating mechanism supported by the chair attachment means for guided forward and rearward movement in relation to the chair attachment means, a foot rest including a foot rest platform and at least two foot rest platform support arms each having a first and second end. The first end of the support arms is attached to the foot rest platform and the second ends of the support arms are attached to the foot rest actuating mechanism. The support arms moveably suspend the foot rest platform in relation to the chair seat. Pivot means pivotally connect the second ends of at least two foot rest platform support arms to the chair attachment means.

Abstract: A memory controller and method of operation for detecting different type of dynamic random access memory (DRAM) devices in a computer system. The memory controller has capabilities for improved page hits which cause the row address strobe signals to remain asserted following certain cycles. A mechanism in the memory controller selectably disables column address strobing. Different DRAM types are distinguishable by reading back data previously written to a memory location. Data is written to memory with a cycle causing the memory controller to keep the row address strobes asserted. Column address strobing is disabled. A read back cycle is performed without column address strobing. If data is present, the DRAM is an extended data output (EDO) DRAM. If data is not present, the DRAM is a fast page mode DRAM.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When a PCI device executes a memory read, the processor cache and L2 cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: In a microcomputer system implementing cache memory, the microprocessor can execute back-to-back pipelined burst operations without corrupting the internal address of the cache memory. The address strobe from the processor is blocked by the cache memory controller, allowing a burst operation to complete from or to the cache memories before the second address is strobed into the cache.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the Peripheral Component Interconnect (PCI) to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: An arbiter circuit for controlling access to the main memory for requests asserted by the microprocessor, the refresh controller and PCI bus masters. Generally, the priority of the memory requests are as follows, with some exceptions: (1) second refresh request; (2) processor-to-memory write request; (3) memory-to-processor read request; (4) PCI-to-memory write request; (5) memory-to-PCI read request; and (6) first refresh request. The second refresh request indicates that two refreshes are outstanding. When that occurs, both outstanding refresh requests are assigned the highest priority. The processor-to-memory write request is always higher in priority than other memory requests except the second refresh. However, under certain conditions, the processor-to-memory write requests is held off to allow other cycles to proceed. The memory-to-processor read request is generally higher in priority than the PCI write and read requests, unless certain conditions occur to override that priority.

Abstract: An adjustable chair comprises a front seat assembly, a rear seat assembly, and a base assembly, the base assembly supporting the front and rear seat assemblies independently of one another. The front seat assembly has a front seat pivotally mounted for rotation about a horizontal axis. The rear seat assembly has a rear seat pivotally mounted for rotation about a horizontal axis The two rotation axis are separated from one another a sufficient distance that a person may sit on the front seat and position his or her back against the rear seat. Each seat is pivotally mounted by its respective seat assembly means such that the rotation axis for each seat is located at a fulcrum point from which the seat is pivotally supported.

Abstract: An adjustable chair comprises a front seat assembly, a rear seat assembly, and a base assembly, the base assembly supporting the front and rear seat assembly independently of one another. The front seat assembly has a front seat pivotally mounted for rotation about a horizontal axis. The rear seat assembly has a rear seat pivotally mounted for rotation about a horizontal axis. The two rotation axes are separated from one another a sufficient distance that a person may sit on the front seat and position his or her back against the rear seat. Each seat is pivotally mounted by its respective seat assembly such that the rotation axis for each seat is located at a fulcrum point from which the seat is pivotally supported.