Abstract: An improved vocoder system and method for estimating pitch in a speech waveform which more accurately disregards false pitch estimates resulting from secondary excitations. The vocoder system first performs a correlation calculation on a speech frame and generates an estimated pitch value. The present invention then compares the estimated or determined pitch with a threshold value to determine if the determined or estimated pitch has a suspiciously low pitch value. If so, the present invention performs error checking to disregard pitch estimates that are the result of the First Formant frequency's contribution to the pitch estimation process. The error checking involves examining the higher multiples of the determined pitch value to ascertain whether the determined pitch value might be incorrect. The present invention determines whether one or more higher multiples are missing, whether the higher multiples are related by a common factor, and whether adjacent multiples have missing peaks.

Abstract: A processor employing a dynamically configurable bus interconnect is provided. The interconnect routes data between functional units and memories included within the processor in response to an instruction field. As opposed to a particular hard-wired interconnect, the dynamically variable interconnect may be modified to form an optimum interconnect for the particular algorithm being executed. Still further, the interconnect may be modified between several configurations during the execution of the algorithm, as often as each clock cycle. Because an instruction field is used to directly specify the configuration of the interconnect during execution of that instruction, control over the interconnect is afforded to the programmer writing the code which implements a particular algorithm.

Abstract: A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a pattern recognition detector which stores instruction sequences which implement DSP functions. The pattern recognition detector compares each pattern with an instruction sequence and determines if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the preprocessor converts or maps the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction.

Abstract: A DSP including a register file connected to data memories and functional units is provided. Functional units read operands from the register file and store results into the register file. Various register storage locations form communicative links between the functional units and the memories, in accordance with a particular code sequence being executed by the DSP. Because each functional unit has an independent path to the register file, each functional unit may provide results to the register file concurrently. Additionally, having multiple register storage locations which are accessible to any functional unit permits flexibility in the operation of the DSP. Multiple register storage locations may be used by the same functional unit, allowing program code to be more optimized by storing values for later use in one of the register storage locations, as opposed to storing values in the data memories.

Abstract: A conversion system using a lookup table of adjustment values for converting non-linear, logarithmic pcm codes between attenuated and unattenuated formats. A computer accesses attenuated pcm codes from a compression device, such as that found in the transmit portion of a digital speakerphone, and retrieves an adjustment value from the lookup table using the measured pcm code and a gain code. The gain code corresponds to a gain setting asserted by the computer to a gain device in the transmit portion of the speakerphone. The lookup table is preferably implemented in hardware, such as a ROM, RAM, PLA or similar type device, or is implemented in software or firmware executed by the computer. The retrieved adjustment value is added to the attenuated pcm code to determine the corresponding unattenuated pcm code.

Abstract: An improved vocoder system and method for estimating pitch in a speed waveform. The method comprises an improved correlation method for estimating the pitch parameter which more accurately disregards false correlation peaks resulting from the contribution of the First Formant to the pitch estimation method. The vocoder performs a correlation calculation on a frame of the speech waveform to estimate the pitch of the frame. According to the invention, during the correlation calculation the vocoder performs calculations to determine when a transition from unvoiced to voiced speech occurs. When such a transition is detected, the vocoder widens the correlation sample window. The present invention thus determines when a transition from unvoiced to voiced speech occurs and dynamically adjusts or widens the sample window to reduce the effect of the first Formant in the pitch estimation. Once this frame and the next have been classified as voiced, the correlation sample window can be reduced to its original value.

Abstract: An improved dual tone multifrequency (DTMF) or multitone signal detector which more efficiently and reliably detects DTMF signals. The present invention performs twist computations only when the signal has become stable, thus achieving more accuracy and reliability. The DTMF detector receives a plurality of digital samples of a received signal and calculates energy values for each of the plurality of different uncorrelated frequencies. The DSP then determines maximum values of the energy values for each of the two or more frequency groups, referred to as M(1) and M(2), to detect the plurality of tones in the received signal. The DTMF detector then performs improved twist computation and thresholding. The DTMF detector first determines if the M(1) and M(2) values of the respective frame being examined have the same indices.

Abstract: An improved dual tone multifrequency (DTMF) signal detector which uses the Goertzel DFT algorithm and which utilizes variable or differing frame widths that are frequency dependent for improved detection and reduced error. The DTMF detector includes a codec receiver which receives signals from the transmission media, and a digital signal processor (DSP) coupled to the codec. The DSP receives the digital samples and preferably applies the Goertzel DFT algorithm using differing frame lengths according to the present invention. The DTMF detector utilizes a different frame width for different tones of the possible tone frequencies according to the present invention. Thus the calculation uses a different frame length N for different ones of the uncorrelated frequencies, wherein the different frame lengths comprise at least a subset N of the number of digital samples. The different frame lengths N are designed to optimally align the calculated frequency spectrum at each of the different uncorrelated frequencies.

Abstract: An integrated circuit especially suitable for incorporation into the base and handset units of a cordless telephone integrates the speech, control channels, and microcontroller portions of a modem, and the man-machine interface functions of a cordless telephone. The integrated circuit includes one or more of a number of aspects including an in-circuit emulation mechanism, a simplified keypad reporting mechanism, advanced noise suppression mechanisms, a low power emergency mode mechanism, a low cost serial control bus, a port pin interrupt mechanism, advanced power saving mechanisms, spectral measurement test mode means, a novel shut down mechanism, and a pull-up disabling mechanism.

Abstract: An apparatus and method are provided for discriminating noise in a received signal. The apparatus comprises a first signal processing means, a second signal processing means, a threshold generating means for generating a threshold value. The first signal processing means generates iteration signal samples and predicted iteration signal samples, compares the iteration signal samples and predicted signal samples to generate a predicted error parameter. The second signal processing means generates a threshold adjustment value based on generated successive iteration signal samples. A logic means logically treats the prediction error parameter, the threshold adjustment value and the threshold value to generate a noise indication value.

Abstract: An apparatus and method for discriminating and suppressing noise within an incoming signal including a first signal processor to generate a first signal representing the incoming signal; a second signal processor to generate a second signal representing the first signal; a prediction device which generates a prediction for the second signal; a logic device which determines the difference between the second signal and the prediction and generates a logic output having a first value when the difference exceeds a threshold and a second value when the difference does not exceed the threshold; and a muting device to mute the incoming signal when the logic output has one value and not mute the incoming signal when the logic output has the other value.

Abstract: An apparatus and method for discriminating and suppressing noise within an incoming signal which provide a first signal processing unit for processing the incoming signal to generate a first iteration signal representing average difference signal level of the incoming signal; a second signal processing unit for processing the first iteration signal to generate a second iteration signal representing specified aspects of the first iteration signal; a prediction unit for generating a predicted value for the second iteration signal from earlier samples of the second iteration signal; a logic unit for determining a threshold difference between the second iteration signal and the predicted value, the logic unit generating a logic output having a first value when the threshold difference exceeds a predetermined threshold value and having a second value when the threshold difference does not exceed the predetermined threshold value; and a muting unit for muting signals which is operatively connected to receive the in

Abstract: An apparatus for processing a received signal according to a digital signal processing algorithm having a multiplier and a limit and quantization circuit appropriately connected within the apparatus to permit operation of the multiplier and the limit and quantization circuit in parallel with logic processing by the apparatus. The address bus system of the apparatus is connected to the parallel-connected components and conveys instructions to the parallel-connected components, at least in part, by predetermined address information via the address bus system.

Abstract: A method and apparatus provide a noise detector generating a logic output indicating presence of noise in an incoming signal and an attenuation controller for providing a stepped-response to noise operatively connected to respond to the logic output to record a count of noise detections.

Abstract: The present invention provides an apparatus and method for generating a covariance matrix. According to one aspect of the invention, an apparatus is provided which generally includes a memory, a circular buffer, a multiply-accumulator, and an arithmetic logic unit. The memory contains an array of values representative of a plurality of samples, and the circular buffer is configured to provide a predetermined number of memory locations. A method for generating the covariance matrix is further provided which uses the architecture listed above to efficiently generate a covariance matrix based on the values in the memory. In one aspect of the invention, the method provides that the memory, the circular buffer, the multiply-accumulator, and the arithmetic logic unit, all operate in parallel to fully exploit the resources provided by the architecture.

Abstract: An arithmetic logic unit includes first and second buses for efficient operations upon multiple-bit operands. The arithmetic logic unit includes, in addition to the first and second buses, a shift register having an input coupled to the first bus and an output, a summer having a first input coupled to the shift register output, a second input coupled to the second bus, and an output, and an accumulator having an input coupled to the summer output and an output coupled to the first bus. The arithmetic logic unit further includes a buffer having an input also coupled to the summer output and an output coupled to the second bus. The summer provides two's compliment inversion when required and the shift register performs sign bit force zero, right shifting, and masking operations. In addition, an overflow detector and overflow correction detect and correct overflow conditions without requiring additional operating cycles.

Abstract: An apparatus adaptable for use with a digital-analog conversion device for effecting communications from a digital device to an analog device, having a digital-analog circuit for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the digital-analog device. The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of interpolation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of interpolation.

Abstract: An apparatus adaptable for use with an analog-digital conversion device for effecting communications between an analog device and a digital device, the analog-digital conversion device converting incoming analog signals received from the analog device to incoming digital signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device.The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation.

Abstract: An apparatus adaptable for use with an analog-digital-analog conversion device for effecting communications between an analog device and a digital device, the analog-digital-analog conversion device converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device.The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation and a specified number of iterations of interpolation.

Abstract: An apparatus adaptable for use in effecting communications between an analog device and a digital device, having an analog-digital-analog circuit for converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device. The analog-digital-analog device includes a single digital-to-analog converter and switches for selectively configuring the analog-digital-analog circuit to effect conversion of incoming analog signals to incoming digital signals or, alternatively, to effect conversion of interpolated outgoing digital signals to outgoing analog signals.