Patents by Inventor John G. Bartkowiak

John G. Bartkowiak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System for detecting and correcting errors generated by arithmetic logic units
    Patent number: 4994993
    Abstract: Apparatus is provided for performing a method for detecting and correcting errors in one clock cycle that occur during arithmetic operations of at least two operands. Specifically, two operands are operated on to obtain a result. The digits of the result are added to one another. This adding step is repeated until a first single digit is achieved. The digits of each of the operands are added to one another to obtain an intermediate sum. The digits of the intermediate sum, in turn, are added to one another. Once again, this operation is repeated until a second single digit is achieved. The first single digit number is compared with the second single digit number and a signal indicative of error is generated if the comparison is unsuccessful.In order to correct the error, the digits of each of the operands are added to one another to obtain an intermediate sum. Sequentially, a digit is subtracted from the partial sum of the remaining digits of each of the operands.
    Type: Grant
    Filed: October 25, 1988
    Date of Patent: February 19, 1991
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Safdar M. Asghar, John G. Bartkowiak, Eric A. Suss