Patents by Inventor John Hopkins
John Hopkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190103410Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: INTEL CORPORATIONInventors: DAVID A. DAYCOCK, PURNIMA NARAYANAN, JOHN HOPKINS, GUOXING DUAN, BARBARA L. CASEY, CHRISTOPHER J. LARSEN, MENG-WEI KUO, QIAN TAO
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Publication number: 20190066016Abstract: A device may detect a trigger to perform a benchmarking task. The benchmarking task may include a first benchmarking of a first resource utilization associated with one or more tasks completed via an automated procedure. The benchmarking task may include a second benchmarking of a second resource utilization associated with the one or more tasks completed via a manual procedure. The device may determine project data relating to a project platform based on detecting the trigger to perform the benchmarking task. The device may process the project data relating to the project platform to benchmark the project. The device may generate a recommendation relating to completion of the one or more tasks using the automated procedure or the manual procedure. The device may communicate with one or more other devices to perform a response action based on the recommendation.Type: ApplicationFiled: December 15, 2017Publication date: February 28, 2019Inventors: Bhaskar GHOSH, Mohan Sekhar, Vijayaraghavan Koushik, John Hopkins, Rajendra T. Prasad, Mark Lazarus, Krupa Srivastava
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Patent number: 10217755Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.Type: GrantFiled: April 1, 2017Date of Patent: February 26, 2019Assignee: Intel CorporationInventors: Changhan Kim, Kunal Shrotri, John Hopkins, Darwin Franseda Fan
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Publication number: 20190013329Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.Type: ApplicationFiled: August 24, 2018Publication date: January 10, 2019Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
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Patent number: 10170491Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.Type: GrantFiled: January 19, 2017Date of Patent: January 1, 2019Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, John Hopkins, Srikant Jayanti
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Patent number: 10170639Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.Type: GrantFiled: January 4, 2016Date of Patent: January 1, 2019Assignee: Micron Technology, Inc.Inventors: John Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti
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Patent number: 10157405Abstract: Embodiments disclosed herein may include a system including a server configured to receive from the mobile device the digital image capturing the object, execute an object recognition protocol to identify one or more image features of the digital image, determine an identification of the object based upon the one or more features of the digital image identified by the executed object recognition protocol, generate an object profile of the object based upon one or more data records of the object stored in the system databases where each respective record containing at least one data point corresponding to a valuation of the respective object, determine a value of the data point based upon the valuation of the respective object and a characteristic of a member, and transmit to the mobile device the object profile for the object captured in the digital image.Type: GrantFiled: April 18, 2016Date of Patent: December 18, 2018Assignee: United Services Automobile AssociationInventor: John Hopkins
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Publication number: 20180350827Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.Type: ApplicationFiled: May 15, 2018Publication date: December 6, 2018Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
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Publication number: 20180315766Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.Type: ApplicationFiled: July 5, 2018Publication date: November 1, 2018Inventors: Hongbin Zhu, Zhenyu Lu, Gordon Haller, Jie Sun, Randy J. Koval, John Hopkins
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Publication number: 20180294272Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.Type: ApplicationFiled: October 30, 2017Publication date: October 11, 2018Applicant: Intel CorporationInventors: Darwin Fan, Sateesh Koka, Gordon Haller, John Hopkins, Shyam Surthi, Anish Khandekar
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Patent number: 10096610Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. A first portion of the plurality of doped semiconductor material layers may be doped with a first dopant having a first dopant parameter. A second portion of the plurality of doped semiconductor material layers may be doped with a second dopant having a second dopant parameter. In embodiments, the first portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than a defined threshold. In embodiments, the second portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than the defined threshold. The differing dopant concentrations have been found to beneficially and advantageously affect the etch rate in the respective semiconductor layers when forming control gate recesses in the semiconductor layers.Type: GrantFiled: September 29, 2017Date of Patent: October 9, 2018Assignee: Intel CorporationInventors: John Hopkins, Younghee Kim, Jie Li, Yu Yuwen, Ramey Abdelrahaman, Kunal Shrotri
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Publication number: 20180286876Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.Type: ApplicationFiled: April 1, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Changhan Kim, Kunal Shrotri, John Hopkins, Darwin Franseda Fan
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Patent number: 10090317Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.Type: GrantFiled: July 27, 2016Date of Patent: October 2, 2018Assignee: Micron Technology, Inc.Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
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Patent number: 10079246Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.Type: GrantFiled: December 20, 2017Date of Patent: September 18, 2018Assignee: Micron Technology, Inc.Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
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Patent number: 10038002Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.Type: GrantFiled: October 18, 2016Date of Patent: July 31, 2018Assignee: Micron Technology, Inc.Inventors: Hongbin Zhu, Zhenyu Lu, Gordon Haller, Jie Sun, Randy J. Koval, John Hopkins
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Patent number: 9991273Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.Type: GrantFiled: August 30, 2017Date of Patent: June 5, 2018Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
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Publication number: 20180138196Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.Type: ApplicationFiled: December 20, 2017Publication date: May 17, 2018Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
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Publication number: 20180108669Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.Type: ApplicationFiled: October 18, 2016Publication date: April 19, 2018Inventors: Hongbin Zhu, Zhenyu Lu, Gordon Haller, Jie Sun, Randy J. Koval, John Hopkins
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Patent number: 9853046Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.Type: GrantFiled: June 6, 2016Date of Patent: December 26, 2017Assignee: Micron Technology, Inc.Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
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Publication number: 20170365615Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.Type: ApplicationFiled: August 30, 2017Publication date: December 21, 2017Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat