Patents by Inventor John Hopkins

John Hopkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9847340
    Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Darwin Fan, Sateesh Koka, Gordon Haller, John Hopkins, Shyam Surthi, Anish Khandekar
  • Patent number: 9793282
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 17, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 9754952
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Publication number: 20170200801
    Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventors: John Hopkins, Darwin Franseda Fan
  • Publication number: 20170133392
    Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Inventors: Fatma Arzum Simsek-Ege, John Hopkins, Srikant Jayanti
  • Patent number: 9608000
    Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: March 28, 2017
    Assignee: Micron Technology, Inc.
    Inventors: John Hopkins, Darwin Franseda Fan
  • Patent number: 9559109
    Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: January 31, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, John Hopkins, Srikant Jayanti
  • Patent number: 9530683
    Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 27, 2016
    Assignee: Micron Technology, Inc.
    Inventors: John Hopkins, James Matthew, Jie Sun, Gordon Haller
  • Publication number: 20160351580
    Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 1, 2016
    Inventors: John Hopkins, Darwin Franseda Fan
  • Publication number: 20160336341
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Application
    Filed: July 27, 2016
    Publication date: November 17, 2016
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Patent number: 9478643
    Abstract: A memory structure having at least substantially aligned floating and control gates. Such a memory structure can include a control gate material disposed between a first insulator layer and a second insulator layer, a floating gate material disposed between the first insulator layer and the second insulator layer and at least substantially aligned with the control gate material, the floating gate material including a metal region, and an interpoly dielectric (IPD) layer disposed between the control gate material and the floating gate material such that the IPD layer electrically isolates the control gate material from the floating gate material.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: John Hopkins, Fatma A. Simsek-Ege
  • Publication number: 20160284728
    Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
  • Patent number: 9431410
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: August 30, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Patent number: 9397210
    Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: July 19, 2016
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Patent number: 9362300
    Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 7, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
  • Publication number: 20160133752
    Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.
    Type: Application
    Filed: January 4, 2016
    Publication date: May 12, 2016
    Inventors: John Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti
  • Publication number: 20160104717
    Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 14, 2016
    Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
  • Publication number: 20160054900
    Abstract: An Internet based computer-implemented method for generating and displaying an image of an object on a users computer screen, wherein said image may be rotated 360° about a horizontal axis and 360° about a vertical axis, the method comprising the steps of: accessing a database of digital images or a product; evaluating said user's computer hardware parameters, where said parameters are selected from the group consisting of Internet connection speed, Internet connection type, type of computing device, and type of Internet browser software; determining the dimensions of the display field of the computing device; determining a sharp image size, a spin image size, and a zoom image size; loading a subset of said images; accepting user instructions selected from the group consisting of spin and zoom; and displaying on images pursuant to said user instructions while loading additional images not included in said subset of images.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 25, 2016
    Inventors: Chuck Surack, John Hopkins, Michael Ross, Mike Clem, Greg Wardwell, Dan Schafer
  • Publication number: 20160055154
    Abstract: A computer implemented method for searching an electronic database of product images, said method comprising the steps of: accessing a plurality of digital images of each of a plurality of products; segregating said images by color and product type; calculating the number of pixels for each color in each of said product images; dividing said colors into a plurality of discrete segments within the visible color spectrum; averaging the number of pixels for each color for each said image of a single product; applying a multiplier to blocks that exist within a cohesive quantized color group; normalizing said pixel count based on the percentage of the number of pixels within a predetermined range; storing said histogram into a database wherein each discrete segment has one value within the visual spectrum; and sorting the histograms in order of highest percentage of each color in the profile to lowest.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: Chuck Surack, John Hopkins, Michael Ross, Mike Clem, Greg Wardwell, Dan Schafer
  • Publication number: 20160049417
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Application
    Filed: October 28, 2015
    Publication date: February 18, 2016
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat