Patents by Inventor John J. Konrad

John J. Konrad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8288266
    Abstract: A method of making a circuitized substrate in which the substrate includes circuit elements having exposed surfaces defined by two thin layers of permanent photoimaged solder mask material which are applied through fine mesh screens. The use of two thin layers assures effective coverage of the material to precisely expose the desired surfaces in high-density circuit patterns. A circuitized substrate assembly and an information handling system adapted for having one or more such assemblies therein are also provided.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: October 16, 2012
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Norman A. Card, Richard A. Day, John J. Konrad
  • Publication number: 20120243155
    Abstract: A method of forming a circuitized substrate utilizing a conductive nub structure for enhanced interconnection integrity by using a joining core layer with copper outer layer on it, and forming thru-holes in the joining layer. Placing conductive adhesive in the thru-hole prior to removing the copper outer layers from the joining core layer creates an adhesive bump on joining core layer that engages a conductive secondary metal nub placed on the circuitized substrate-to-joining layer contact points, thus creating an enhanced connection between the layers.
    Type: Application
    Filed: January 20, 2011
    Publication date: September 27, 2012
    Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
    Inventors: Luis J. Matienzo, Norman A. Card, Daniel C. VanHart, John J. Konrad, Frank D. Egitto, Rabindra N. Das
  • Patent number: 7910156
    Abstract: A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: March 22, 2011
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Norman A. Card, Robert J. Harendza, John J. Konrad, Tonya L. Mosher, Susan Pitely, Jose A. Rios
  • Patent number: 7635552
    Abstract: A photoresist composition, e.g., a positive acting resist, for use in the formation of circuit patterns and the like on printed circuit boards and the like circuitized substrates, the photoresist composition including a quantity of silver therein in a sufficient amount to substantially prevent bacteria formation within said composition. A method of making the composition is also provided.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: December 22, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Ross W. Keesler, John J. Konrad, Roy H. Magnuson, Robert A. Sinicki
  • Publication number: 20080241359
    Abstract: A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Norman A. Card, Robert J. Harendza, John J. Konrad, Tonya Mosher, Susan Pitely, Jose A. Rios
  • Patent number: 7425256
    Abstract: An apparatus and method for plating a workpiece. The apparatus comprises, generally, an anode, a cathode, and a selective anode shield/material flow assembly. In use, both the anode and the cathode are immersed in a solution, and the cathode is used to support the workpiece. During an electroplating process, the anode and the cathode generate an electric field emanating from the anode towards the cathode, to generate a corresponding current to deposit an electroplating material on the workpiece. The selective shield/material flow assembly is located between the anode and the cathode, and forms a multitude of adjustable openings. These opening have sizes that are adjustable during the electroplating process for selectively and controllably adjusting the amount of electric flux passing through the selective shield/material flow assembly and the distribution of the electroplating material on the workpiece. The selective shield/material flow assembly can also be used with an electroless plating system.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: September 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Barrese, Gary Gajdorus, Allen H. Hopkins, John J. Konrad, Robert C. Schaffer, Timothy L. Wells
  • Publication number: 20080038670
    Abstract: A method of making a circuitized substrate in which the substrate includes circuit elements having exposed surfaces defined by two thin layers of permanent photoimaged solder mask material which are applied through fine mesh screens. The use of two thin layers assures effective coverage of the material to precisely expose the desired surfaces in high-density circuit patterns. A circuitized substrate assembly and an information handling system adapted for having one or more such assemblies therein are also provided.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 14, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Norman A. Card, Richard A. Day, John J. Konrad
  • Publication number: 20080026316
    Abstract: A photoresist composition, e.g., a positive acting resist, for use in the formation of circuit patterns and the like on printed circuit boards and the like circuitized substrates, the photoresist composition including a quantity of silver therein in a sufficient amount to substantially prevent bacteria formation within said composition. A method of making the composition is also provided.
    Type: Application
    Filed: July 25, 2006
    Publication date: January 31, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Ross W. Keesler, John J. Konrad, Roy H. Magnuson, Robert A. Sinicki
  • Patent number: 7288177
    Abstract: An apparatus and method for plating a workpiece. The apparatus comprises, generally, an anode, a cathode, and a selective anode shield/material flow assembly. In use, both the anode and the cathode are immersed in a solution, and the cathode is used to support the workpiece. During an electroplating process, the anode and the cathode generate an electric field emanating from the anode towards the cathode, to generate a corresponding current to deposit an electroplating material on the workpiece. The selective shield/material flow assembly is located between the anode and the cathode, and forms a multitude of adjustable openings. These opening have sizes that are adjustable during the electroplating process for selectively and controllably adjusting the amount of electric flux passing through the selective shield/material flow assembly and the distribution of the electroplating material on the workpiece. The selective shield/material flow assembly can also be used with an electroless plating system.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Barrese, Gary Gajdorus, Allen H. Hopkins, John J. Konrad, Robert C. Schaffer, Timothy L. Wells
  • Patent number: 7169313
    Abstract: A method of plating a circuit pattern on a substrate to produce a circuitized substrate (e.g., a printed circuit board) in which a dual step metallurgy application process is used in combination with a dual step photo-resist removal process. Thru-holes are also possible, albeit not required.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: January 30, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Norman A. Card, Robert D. Edwards, John J. Konrad, Roy H. Magnuson, Timothy L. Wells, Michael Wozniak
  • Patent number: 7163847
    Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: January 16, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
  • Patent number: 7091066
    Abstract: A method of making a circuitized substrate in which a commoning bar, used during the plating of the circuitry on the substrate and coupled to a second set of conductors which in turn are coupled to a first set of conductors, is terminated from the second set of conductors.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: August 15, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
  • Patent number: 7087441
    Abstract: A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different metal or metal alloy composition. In each embodiment, a single commoning layer (e.g., copper) is used, being partially removed following the first deposition. The solder is deposited using an electroplating process (electroless or electrolytic) and the commoning bar in both depositing steps. An information handling system utilizing the circuitized substrate formed in accordance with the invention is also described.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: August 8, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John J. Konrad, Joseph A. Kotylo, Jose A. Rios
  • Patent number: 7084014
    Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: August 1, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Timothy Antesberger, James W. Fuller, Jr., John J. Konrad, John Kresge, Stephen Krasniak, Timothy L. Wells
  • Patent number: 7007378
    Abstract: A process for manufacturing a land grid array connector for a printed wiring board is disclosed. The process does not require electroplating precious metal overlays. Therefore, no commoning bar is required. Another benefit of the invention includes a connector design using only a flash, soft gold application in the outer surface of the connector. Physical hardness and durability are derived from a thin palladium layer lying beneath the flash gold layer.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: March 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: John G. Gaudiello, James D. Herard, John J. Konrad, Jeffrey McKeveny, Timothy L. Wells
  • Patent number: 6931722
    Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: August 23, 2005
    Assignee: International Business Machines Corporation
    Inventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
  • Patent number: 6746578
    Abstract: An apparatus and method for plating a workpiece. The apparatus comprises, generally, an anode, a cathode, and a selective anode shield/material flow assembly. In use, both the anode and the cathode are immersed in a solution, and the cathode is used to support the workpiece. During an electroplating process, the anode and the cathode generate an electric field emanating from the anode towards the cathode, to generate a corresponding current to deposit an electroplating material on the workpiece. The selective shield/material flow assembly is located between the anode and the cathode, and forms a multitude of adjustable openings. These opening have sizes that are adjustable during the electroplating process for selectively and controllably adjusting the amount of electric flux passing through the selective shield/material flow assembly and the distribution of the electroplating material on the workpiece. The selective shield/material flow assembly can also be used with an electroless plating system.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: June 8, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Barrese, Gary Gajdorus, Allen H. Hopkins, John J. Konrad, Robert C. Schaffer, Timothy L. Wells
  • Publication number: 20030177635
    Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 25, 2003
    Inventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A. Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
  • Patent number: 6586683
    Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A. Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
  • Publication number: 20030102160
    Abstract: A process for manufacturing a land grid array connector for a printed wiring board is disclosed. The process does not require electroplating precious metal overlays. Therefore, no commoning bar is required. Another benefit of the invention includes a connector design using only a flash, soft gold application in the outer surface of the connector. Physical hardness and durability are derived from a thin palladium layer lying beneath the flash gold layer.
    Type: Application
    Filed: December 12, 2002
    Publication date: June 5, 2003
    Applicant: International Business Machines Corporation
    Inventors: John G. Gaudiello, James D. Herard, John J. Konrad, Jeffrey McKeveny, Timothy L. Wells