Patents by Inventor John L. Gustafson
John L. Gustafson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200312731Abstract: Methods and systems to improve printed electrical components and for integration in circuits are disclosed. Passive components, e.g., capacitors, resistors and inductors, can be printed directly into a solid ceramic block using additive manufacturing. A grounded conductive plane or a conductive cage may be placed between adjacent electrical components, or around each component, to minimize unwanted parasitic effects in the circuits, such as, e.g., parasitic capacitance or parasitic inductance. Resistors may be printed in non-traditional shapes, for example, S-shape, smooth S-shape, U-shape, V-shape, Z-shape, zigzag-shape, and any other acceptable alternative configurations. The flexibility in shapes and sizes of the printed resistors allows optimal space usage of the ceramic block. The present invention also discloses an electrical component comprising combined predetermined values of capacitance, resistance and inductance.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Inventor: John L. Gustafson
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Patent number: 10777366Abstract: Methods of increasing an energy density of an energy storage device involve increasing the capacitance of the energy storage device by depositing a material into a porous structure of the energy storage device using an atomic layer deposition process, by performing a procedure designed to increase a distance to which an electrolyte penetrates within channels of the porous structure, or by placing a dielectric material into the porous structure. Another method involves annealing the energy storage device in order to cause an electrically conductive substance to diffuse to a surface of the structure and form an electrically conductive layer thereon. Another method of increasing energy density involves increasing the breakdown voltage and another method involves forming a pseudocapacitor. A method of increasing an achievable power output of an energy storage device involves depositing an electrically conductive material into the porous structure.Type: GrantFiled: March 26, 2018Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Donald S. Gardner, Zhaohui Chen, Wei C. Jin, Scott B. Clendenning, Eric C. Hannah, Tomm V. Aldridge, John L. Gustafson
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Patent number: 10685892Abstract: Methods and systems to improve printed electrical components and for integration in circuits are disclosed. Passive components, e.g., capacitors, resistors and inductors, can be printed directly into a solid ceramic block using additive manufacturing. A grounded conductive plane or a conductive cage may be placed between adjacent electrical components, or around each component, to minimize unwanted parasitic effects in the circuits, such as, e.g., parasitic capacitance or parasitic inductance. Resistors may be printed in non-traditional shapes, for example, S-shape, smooth S-shape, U-shape, V-shape, Z-shape, zigzag-shape, and any other acceptable alternative configurations. The flexibility in shapes and sizes of the printed resistors allows optimal space usage of the ceramic block. The present invention also discloses an electrical component comprising combined predetermined values of capacitance, resistance and inductance.Type: GrantFiled: September 28, 2019Date of Patent: June 16, 2020Assignee: VQ RESEARCH, INC.Inventor: John L. Gustafson
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Publication number: 20200027802Abstract: Methods and systems to improve printed electrical components and for integration in circuits are disclosed. Passive components, e.g., capacitors, resistors and inductors, can be printed directly into a solid ceramic block using additive manufacturing. A grounded conductive plane or a conductive cage may be placed between adjacent electrical components, or around each component, to minimize unwanted parasitic effects in the circuits, such as, e.g., parasitic capacitance or parasitic inductance. Resistors may be printed in non-traditional shapes, for example, S-shape, smooth S-shape, U-shape, V-shape, Z-shape, zigzag-shape, and any other acceptable alternative configurations. The flexibility in shapes and sizes of the printed resistors allows optimal space usage of the ceramic block. The present invention also discloses an electrical component comprising combined predetermined values of capacitance, resistance and inductance.Type: ApplicationFiled: September 28, 2019Publication date: January 23, 2020Inventor: John L. Gustafson
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Patent number: 10431508Abstract: Methods and systems to improve printed electrical components and for integration in circuits are disclosed. Passive components, e.g., capacitors, resistors and inductors, can be printed directly into a solid ceramic block using additive manufacturing. A grounded conductive plane or a conductive cage may be placed between adjacent electrical components, or around each component, to minimize unwanted parasitic effects in the circuits, such as, e.g., parasitic capacitance or parasitic inductance. Resistors may be printed in non-traditional shapes, for example, S-shape, smooth S-shape, U-shape, V-shape, Z-shape, zigzag-shape, and any other acceptable alternative configurations. The flexibility in shapes and sizes of the printed resistors allows optimal space usage of the ceramic block. The present invention also discloses an electrical component comprising combined predetermined values of capacitance, resistance and inductance.Type: GrantFiled: December 13, 2016Date of Patent: October 1, 2019Assignee: VQ RESEARCH, INC.Inventor: John L. Gustafson
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Publication number: 20190287725Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layers and termination caps comprising a base metal may be cladded with a noble metal to lower costs without the tendency of base metal atoms combining with oxygen atoms in the dielectric material as the base metal does not physically contact the dielectric material. The conductive layers may comprise a wavy shape, and may comprise conductive layer ends modified to minimize or eliminate sharp edges and corners, such as comprising a convex, wavy, or bulbous shape. The noble metal portion of a conductive layer may be a minimum thickness required to prevent chemical reactions between the base metal portion and the dielectric material. In conjunction with computer modeling of Laplace's equation, the conductors can be reshaped at little material cost to make the electric field nearly uniform through adjustments of the base metal portion.Type: ApplicationFiled: May 24, 2019Publication date: September 19, 2019Inventor: John L. Gustafson
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Publication number: 20190214195Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layer ends of a multilayer ceramic capacitor may be modified to comprise a round shape, which may increase structural stability of the capacitor's layers. Other configurations may be possible, such as bulbous or wavy shaped conductive layer ends. The layers may comprise one or more pillars made from dielectric material, e.g., barium titanate, disposed through a portion of a conductive layer. The dielectric material may be the same material used in the insulator layers of the capacitor. Each pillar may comprise a plurality of spot connections surrounding its perimeter. The embedded pillars may be used to prevent delamination of the layers and to increase mechanical strength. Additionally, an algorithm of a computing device may determine an optimal shape, size, and/or configuration of the capacitor based on one or more predetermined specifications or properties.Type: ApplicationFiled: March 19, 2019Publication date: July 11, 2019Inventor: John L. Gustafson
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Publication number: 20190214196Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layer ends and dielectric layer edges of a multilayer ceramic capacitor may be modified to comprise a round shape, which may increase voltage limits by reducing electric field intensity that results from sharp corners. Further, the capacitor may comprise wave-like structures to increase surface area of a conductive layer and/or dielectric layer. The round shape of the conductive layer end may in-part reduce the need for a wide protective gap due to its dome-shape permitting the dielectric layer to be wider on top and bottom, and thinner at the center, e.g. concave, which provides strength support to the layers. The 3D Printing process permits the distance between the conductive layer end of the conductive layer to be much closer to the dielectric layer edge of the dielectric layer, such as below the standard 500 microns.Type: ApplicationFiled: March 19, 2019Publication date: July 11, 2019Inventor: John L. Gustafson
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Patent number: 10332684Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layers and termination caps comprising a base metal may be cladded with a noble metal to lower costs without the tendency of base metal atoms combining with oxygen atoms in the dielectric material as the base metal does not physically contact the dielectric material. The conductive layers may comprise a wavy shape, and may comprise conductive layer ends modified to minimize or eliminate sharp edges and corners, such as comprising a convex, wavy, or bulbous shape. The noble metal portion of a conductive layer may be a minimum thickness required to prevent chemical reactions between the base metal portion and the dielectric material. In conjunction with computer modeling of Laplace's equation, the conductors can be reshaped at little material cost to make the electric field nearly uniform through adjustments of the base metal portion.Type: GrantFiled: September 23, 2016Date of Patent: June 25, 2019Assignee: VQ RESEARCH, INC.Inventor: John L. Gustafson
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Publication number: 20190103229Abstract: Methods of increasing an energy density of an energy storage device involve increasing the capacitance of the energy storage device by depositing a material into a porous structure of the energy storage device using an atomic layer deposition process, by performing a procedure designed to increase a distance to which an electrolyte penetrates within channels of the porous structure, or by placing a dielectric material into the porous structure. Another method involves annealing the energy storage device in order to cause an electrically conductive substance to diffuse to a surface of the structure and form an electrically conductive layer thereon. Another method of increasing energy density involves increasing the breakdown voltage and another method involves forming a pseudocapacitor. A method of increasing an achievable power output of an energy storage device involves depositing an electrically conductive material into the porous structure.Type: ApplicationFiled: March 26, 2018Publication date: April 4, 2019Inventors: Donald S. Gardner, Zhaohui Chen, Wei C. Jin, Scott B. Clendenning, Eric C. Hannah, Tomm V. Aldridge, John L. Gustafson
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Patent number: 10242803Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layer ends and dielectric layer edges of a multilayer ceramic capacitor may be modified to comprise a round shape, which may increase voltage limits by reducing electric field intensity that results from sharp corners. Further, the capacitor may comprise wave-like structures to increase surface area of a conductive layer and/or dielectric layer. The round shape of the conductive layer end may in-part reduce the need for a wide protective gap due to its dome-shape permitting the dielectric layer to be wider on top and bottom, and thinner at the center, e.g. concave, which provides strength support to the layers. The 3D Printing process permits the distance between the conductive layer end of the conductive layer to be much closer to the dielectric layer edge of the dielectric layer, such as below the standard 500 microns.Type: GrantFiled: August 30, 2016Date of Patent: March 26, 2019Assignee: VQ RESEARCH, INC.Inventor: John L. Gustafson
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Patent number: 10236123Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layer ends of a multilayer ceramic capacitor may be modified to comprise a round shape, which may increase structural stability of the capacitor's layers. Other configurations may be possible, such as bulbous or wavy shaped conductive layer ends. The layers may comprise one or more pillars made from dielectric material, e.g., barium titanate, disposed through a portion of a conductive layer. The dielectric material may be the same material used in the insulator layers of the capacitor. Each pillar may comprise a plurality of spot connections surrounding its perimeter. The embedded pillars may be used to prevent delamination of the layers and to increase mechanical strength. Additionally, an algorithm of a computing device may determine an optimal shape, size, and/or configuration of the capacitor based on one or more predetermined specifications or properties.Type: GrantFiled: January 15, 2017Date of Patent: March 19, 2019Assignee: VQ RESEARCH, INC.Inventor: John L. Gustafson
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Publication number: 20190080847Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Layers of a capacitor may be modified from its traditional planar shape to a wavy structure. The wavy shape increases surface area within a fixed volume of the capacitor, thus increasing capacitance, and may comprise smooth and repetitive oscillations without the presence of voltage-degrading sharp corners. In addition, the ends of each conductive layer do not have sharp edges, such as comprising a round corner. The one-dimensional wave pattern may run parallel to the width of the capacitor, or it may align in parallel to the length of the capacitor. In some embodiments, the wave pattern may be parallel to both the width and the length—in two dimensions—such that it forms an egg-crate shape. Further, the wavy structures may comprise of secondary or tertiary wavy structures to further increase surface area.Type: ApplicationFiled: November 2, 2018Publication date: March 14, 2019Inventor: John L. Gustafson
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Patent number: 10170244Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods may include forming an electrochemical capacitor device by forming pores in low-purity silicon materials. Various embodiments described herein enable the fabrication of high capacitive devices using low cost techniques.Type: GrantFiled: December 27, 2011Date of Patent: January 1, 2019Assignee: INTEL CORPORATIONInventors: Donald S. Gardner, Cary L. Pint, Charles W. Holzwarth, Wei Jin, Zhaohui Chen, Yang Liu, Eric C. Hannah, John L. Gustafson
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Patent number: 10128047Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Layers of a capacitor may be modified from its traditional planar shape to a wavy structure. The wavy shape increases surface area within a fixed volume of the capacitor, thus increasing capacitance, and may comprise smooth and repetitive oscillations without the presence of voltage-degrading sharp corners. In addition, the ends of each conductive layer do not have sharp edges, such as comprising of a round corner. The one-dimensional wave pattern may run parallel to the width of the capacitor, or it may align in parallel to the length of the capacitor. In some embodiments, the wave pattern may be parallel to both the width and the length—in two dimensions—such that it forms an egg-crate shape. Further, the wavy structures may comprise of secondary or tertiary wavy structures to further increase surface area.Type: GrantFiled: July 18, 2016Date of Patent: November 13, 2018Assignee: VQ RESEARCH, INC.Inventor: John L. Gustafson
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Patent number: 10014123Abstract: In one embodiment of the invention, a method of forming an energy storage device is described in which a porous structure of an electrically conductive substrate is measured in-situ while being electrochemically etched in an electrochemical etching bath until a predetermined value is obtained, at which point the electrically conductive substrate may be removed from the electrochemical etching bath. In another embodiment, a method of forming an energy storage device is described in which an electrically conductive porous structure is measured to determine the energy storage capacity of the electrically conductive porous structure. The energy storage capacity of the electrically conductive porous structure is then reduced until a predetermined energy storage capacity value is obtained.Type: GrantFiled: March 9, 2016Date of Patent: July 3, 2018Assignee: INTEL CORPORATIONInventors: Eric C. Hannah, Cary L. Pint, Charles W. Holzwarth, John L. Gustafson
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Patent number: 9978533Abstract: An energy storage device includes a middle section (610) including a plurality of double-sided porous structures (500), each of which contain multiple channels (511) in two opposing surfaces (515, 525) thereof, an upper section (620) comprising a single-sided porous structure (621) containing multiple channels (622) in a surface (625) thereof, and a lower section (630) including a single-sided porous structure (631) containing multiple channels (632) in a surface (635) thereof.Type: GrantFiled: February 21, 2012Date of Patent: May 22, 2018Assignee: Intel CorporationInventors: Donald S. Gardner, Tomm V. Aldridge, Charles W. Holzwarth, Cary L. Pint, Zhaohui Chen, Wei C. Jin, Yang Liu, John L. Gustafson
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Publication number: 20170236644Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layer ends of a multilayer ceramic capacitor may be modified to comprise a round shape, which may increase structural stability of the capacitor's layers. Other configurations may be possible, such as bulbous or wavy shaped conductive layer ends. The layers may comprise one or more pillars made from dielectric material, e.g., barium titanate, disposed through a portion of a conductive layer. The dielectric material may be the same material used in the insulator layers of the capacitor. Each pillar may comprise a plurality of spot connections surrounding its perimeter. The embedded pillars may be used to prevent delamination of the layers and to increase mechanical strength. Additionally, an algorithm of a computing device may determine an optimal shape, size, and/or configuration of the capacitor based on one or more predetermined specifications or properties.Type: ApplicationFiled: January 15, 2017Publication date: August 17, 2017Inventor: John L. Gustafson
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Publication number: 20170092556Abstract: Methods and systems to improve printed electrical components and for integration in circuits are disclosed. Passive components, e.g., capacitors, resistors and inductors, can be printed directly into a solid ceramic block using additive manufacturing. A grounded conductive plane or a conductive cage may be placed between adjacent electrical components, or around each component, to minimize unwanted parasitic effects in the circuits, such as, e.g., parasitic capacitance or parasitic inductance. Resistors may be printed in non-traditional shapes, for example, S-shape, smooth S-shape, U-shape, V-shape, Z-shape, zigzag-shape, and any other acceptable alternative configurations. The flexibility in shapes and sizes of the printed resistors allows optimal space usage of the ceramic block. The present invention also discloses an electrical component comprising combined predetermined values of capacitance, resistance and inductance.Type: ApplicationFiled: December 13, 2016Publication date: March 30, 2017Inventor: John L. Gustafson
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Publication number: 20170018366Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layers and termination caps comprising a base metal may be cladded with a noble metal to lower costs without the tendency of base metal atoms combining with oxygen atoms in the dielectric material as the base metal does not physically contact the dielectric material. The conductive layers may comprise a wavy shape, and may comprise conductive layer ends modified to minimize or eliminate sharp edges and corners, such as comprising a convex, wavy, or bulbous shape. The noble metal portion of a conductive layer may be a minimum thickness required to prevent chemical reactions between the base metal portion and the dielectric material. In conjunction with computer modeling of Laplace's equation, the conductors can be reshaped at little material cost to make the electric field nearly uniform through adjustments of the base metal portion.Type: ApplicationFiled: September 23, 2016Publication date: January 19, 2017Inventor: John L. Gustafson