Patents by Inventor John Leonard Sudijono

John Leonard Sudijono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230100602
    Abstract: A method for cleaning contacts on a substrate incorporates ion control to selectively remove oxides. The method includes exposing the substrate to ions of an inert gas, supplying a first RF frequency of a first bias power supply to a substrate support, supplying a second RF frequency of a second bias power supply to a substrate support, and adjusting a first power level of the first RF frequency and a second power level of the second RF frequency to selectively remove oxide from at least one contact on the substrate while inhibiting sputtering of polymer material wherein the oxide removal is selective over removal of polymer material surrounding the at least one contact.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Tuck Foong KOH, John Leonard SUDIJONO
  • Publication number: 20230100863
    Abstract: Methods and apparatus for processing a substrate area provided herein. For example, methods for enhancing surface hydrophilicity on a substrate comprise a) supplying, using a remote plasma source, water vapor plasma to a processing volume of a plasma processing chamber to treat a bonding surface of the substrate, b) supplying at least one of microwave power or RF power at a frequency from about 1 kHz to 10 GHz and a power from about 1 kW to 10 kW to the plasma processing chamber to maintain the water vapor plasma within the processing volume during operation, and c) continuing a) and b) until the bonding surface of the substrate has a hydrophilic contact angle of less than 10°.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Prayudi LIANTO, Yin Wei LIM, James S. PAPANU, Guan Huei SEE, Eric J. BERGMAN, Nur Yasmeen Addina MOHAMED HELMI ISIK, Wei Ying Doreen YONG, Vicknesh SAHMUGANATHAN, Yi Kun Kelvin GOH, John Leonard SUDIJONO, Arvind SUNDARRAJAN
  • Patent number: 7678586
    Abstract: An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: March 16, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Huang Liu, Bei Chao Zhang, Wuping Liu, John Leonard Sudijono, Liang Choo Hsia
  • Patent number: 6987321
    Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: January 17, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Publication number: 20040227247
    Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
    Type: Application
    Filed: November 21, 2003
    Publication date: November 18, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANFACTURING LTD.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Patent number: 6813796
    Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: November 9, 2004
    Assignee: Chartered Semiconductor
    Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
  • Patent number: 6720204
    Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: April 13, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Patent number: 6705512
    Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: March 16, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6692579
    Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: February 17, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho, Subhash Gupta
  • Patent number: 6683002
    Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: January 27, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Publication number: 20030192943
    Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.
    Type: Application
    Filed: April 11, 2002
    Publication date: October 16, 2003
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Publication number: 20030140943
    Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.
    Type: Application
    Filed: February 3, 2003
    Publication date: July 31, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
  • Patent number: 6583069
    Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or organic or inorganic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in a reactor chamber. A key feature of the invention's process is a mole ratio of gas additive to source of silicon, which is maintained in the range of about 0.3-20 depending on the compound used and the deposition process conditions. As a gas additive, one of the group including halide-containing organic compounds having the general formula CxHyRz, and chemical compounds with the double carbon-carbon bonds having the general formula CnH2n, is used.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: June 24, 2003
    Assignee: Chartered Semiconductor Manufacturing Co., Ltd.
    Inventors: Vladislav Y. Vassiliev, John Leonard Sudijono
  • Patent number: 6540841
    Abstract: A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: April 1, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
  • Patent number: 6500771
    Abstract: A method for fabricating a boron-contained silicate glass layers, such as borosilicate and borophosphosilicate glass films at low temperature using High Density Plasma CVD with silane derivatives as a source of silicon, boron and phosphorus compounds as a doping compounds, oxygen is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a flow capability of boron-contained silicate glass materials which provide a film with good film integrity and void-free gap-fill within the steps of device structures after low temperature thermal budget anneal conditions.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: December 31, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Vladislav Vassiliev, John Leonard Sudijono, Alan Cuthbertson
  • Patent number: 6475810
    Abstract: A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: November 5, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu, Simon Chooi, Yakub Aliyu
  • Publication number: 20020100794
    Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
    Type: Application
    Filed: March 15, 2002
    Publication date: August 1, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Publication number: 20020096190
    Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 25, 2002
    Applicant: Chartered Semiconductor Manufacturing Inc.
    Inventors: Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho, Subhash Gupta
  • Patent number: 6417088
    Abstract: A method of forming a conductive cap layer over a metal bonding pad comprises the following steps. A semiconductor structure is provided having an exposed, recessed metal bonding pad within a layer opening. The layer has an upper surface. The exposed metal bonding pad is treated with a solution containing soluble metal ions to form a conductive cap over the metal bonding pad. The conductive cap layer is comprised of the solution metal and has a predetermined thickness. An external bonding element may then be bonded to the conductive cap, forming an electrical connection with the metal bonding pad.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: July 9, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6415973
    Abstract: A method of bonding a bonding element to a metal bonding pad, comprising the following steps. A semiconductor structure having an exposed metal bonding pad within a passivation layer opening is provided. The bonding pad has an upper surface. A bonding element is positioned to contact the bonding pad upper surface. A bonding solution is applied within the passivation layer opening, covering the bonding pad and a portion of the bonding element. The structure is annealed by heating said bonding element to selectively solidify the bonding solution proximate said contact of said bonding element to said bonding pad, bonding the bonding element to the bonding pad.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: July 9, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Mei Sheng Zhou, Yakub Aliyu, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy