Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.

Abstract: An effective copper decontamination method in the fabrication of integrated circuits is achieved. An organic-based HFACAC decontamination compound in vapor phase is sprayed over elemental copper found on equipment or tools or as a spill wherein the compound reacts with all of the elemental copper and forms a volatile compound that can be flushed away thereby completing copper decontamination.

Abstract: A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, and aluminum-copper-silicon is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.

Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or inorganic or organic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as a doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a silicon source to gas additive mole ratio, which is maintained depending on the used compound and deposition process conditions. Inorganic halide-containing compounds are used as gas additives. This feature provides the reaction conditions for the proper reaction performance that allows a deposition of a film with. good film integrity and void-free gap-fill within the steps of device structures.

Abstract: A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. The resulting doped inorganic dielectric layer can reduce copper diffusion without a barrier layer reducing fabrication cost and cycle time, as well as reducing RC delay.

Abstract: An effective copper decontamination method in the fabrication of integrated circuits is achieved. An organic-based HFACAC decontamination compound in vapor phase is sprayed over elemental copper found on equipment or tools or as a spill wherein the compound reacts with all of the elemental copper and forms a volatile compound that can be flushed away thereby completing copper decontamination.

Abstract: A capacitor element of a semiconductor device used for high density semiconductor circuits is formed by the steps of forming the bottom plate of the capacitor, submitting the top of the bottom plate to plasma treatment in an oxidizing medium where nitrogen and oxygen are present, depositing a dielectric layer and submitting the top of the dielectric layer to plasma treatment in an oxidizing medium where nitrogen and oxygen are present. Various materials are used for the plasma treatment in an oxidizing medium where nitrogen and oxygen are present. While the present invention uses amorphous silicon as the dielectric material, plasma treatment in an oxidizing medium where nitrogen and oxygen are present can readily applied to a number of other dielectric materials.

Abstract: A method of fabrication of a metal lines without dishing using damascene and chemical-mechanical polish processes. A Key feature is the hard cap layer that is only formed over the trench opening. The hard cap layer prevents dishing of the metal line and also allows faster CMP than blanket polish stop layers. The method includes forming a first dielectric layer having a first trench opening over a semiconductor structure. A metal layer is deposited in the first trench opening. The metal layer has a dimple. The metal layer is preferably composed of Al or Cu. A hard mask is formed having a first opening over the first trench opening. The first opening is at least partially over first trench opening. A hard cap layer (e.g., W or WSi.sub.x) is selectively deposited on the metal layer exposed in the first opening. The hard cap layer, the hard mask, and the metal layer are chemical-mechanical polished to completely remove the hard mask resulting in a metal line having a "dishing free" flat top surface.