Abstract: Techniques are disclosed for designing a reconfigurable fabric. The reconfigurable fabric is designed using logical elements, configurable connections between and among the logical elements, and rotating circular buffers. The circular buffers contain configuration instructions. The configuration instructions control connections between and among logical elements. The logical elements change operation based on the instructions that rotate through the circular buffers. Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions for the implementation of multiple functions.

Abstract: Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions for the implementation of multiple functions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.

Abstract: Techniques are disclosed for reconfigurable fabric data routing. A plurality of kernels is allocated across a reconfigurable fabric comprised of a plurality of clusters, wherein the plurality of kernels includes at least a first kernel and a second kernel. The first kernel is mounted in a first set of clusters within the plurality of clusters. The second kernel is mounted in a second set of clusters within the plurality of clusters. Available routing is determined through the second set of clusters. A porosity map through the second set of clusters is calculated based on the available routing through the second set of clusters. Data is sent through the second set of clusters to the first set of clusters based on the porosity map. Data input needs are evaluated for the first kernel. The available routing is controlled with instructions in circular buffers within the second set of clusters.

Abstract: Techniques are disclosed for power conservation. A plurality of processing elements and a plurality of instructions are configured. The plurality of processing elements is controlled by instructions contained in a plurality of circular buffers. The plurality of processing elements can comprise a dataflow processor. A first processing element, from the plurality of interconnected processing elements, is set into a sleep state by a first instruction from the plurality of instructions. The first processing element is woken from the sleep state as a result of valid data being presented to the first processing element. A subsection of the plurality of interconnected processing elements is also set into a sleep state based on the first processing element being set into a sleep state.

Abstract: Techniques are disclosed for remote usage of machine learned layers by a second machine learning construct. Layers determined within a first machine learning construct are sent to the second construct. A first data group is obtained in a first locality. The first data group is applied to a first localized machine learning construct. A first set of convolutional layers is determined within the first localized machine learning construct based on the first data group, where the first set of convolutional layers comprises a first data flow graph machine. Similarity is adjudicated between the first localized machine learning construct and a second localized machine learning construct. The first set of convolutional layers is sent to the second localized machine learning construct, based on the similarity that was adjudicated meeting a threshold. A second data group is analyzed by the second localized machine learning construct using the first set of convolutional layers.

Abstract: Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is swapped to storage. The instructions comprise a branchless instruction set. Data stored in circular buffers is paged in and out to a second level memory. State information for each logical element is also saved and restored using paging memory. Instructions are provided to logical elements, such as processing elements, via circular buffers. The instructions enable a group of processing elements to perform operations implementing a desired functionality. That functionality is changed by updating the circular buffers with new instructions that are transferred from paging memory. The previous instructions can be saved off in paging memory before the new instructions are copied over to the circular buffers. This enables the hardware to be rapidly reconfigured amongst multiple functions.

Abstract: Techniques are disclosed for managing data within a reconfigurable computing environment. In a multiple processing element environment, such as a mesh network or other suitable topology, there is an inherent need to pass data between processing elements. Subtasks are divided among multiple processing elements. The output resulting from the subtasks is then merged by a downstream processing element. In such cases, a join operation can be used to combine data from multiple upstream processing elements. A control agent executes on each processing element. A memory buffer is disposed between upstream processing elements and the downstream processing element. The downstream processing element is configured to automatically perform an operation based on the availability of valid data from the upstream processing elements.

Abstract: Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is swapped to storage. Data stored in circular buffers is paged in and out to a second level memory. State information for each logical element is also saved and restored using paging memory. Logical elements such as processing elements are provided instructions via circular buffers. The instructions enable a group of processing elements to perform operations implementing a desired functionality. That functionality is changed by updating the circular buffers with new instructions that are transferred from paging memory. The previous instructions can be saved off in paging memory before the new instructions are copied over to the circular buffers. This enables the hardware to be rapidly reconfigured amongst multiple functions.

Abstract: Techniques are disclosed for circuit configuration. Information is obtained on logical distances between reconfigurable fabric circuits on a semiconductor chip. A plurality of clusters is identified within the reconfigurable fabric circuits on the semiconductor chip. A cycle count separation across the plurality of cluster is evaluated using information on the logical distances. A plurality of counter initializations is calculated where the counter initializations compensate for the cycle count separation across the clusters. A plurality of counters is initialized, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, where the counters are distributed across the clusters, and where the initializing is based on the counter initializations that were calculated. The plurality of counters is started to coordinate configuration across the plurality of clusters.

Abstract: Techniques are disclosed for managing data within a reconfigurable computing environment. In a multiple processing element environment, such as a mesh network, or other suitable topology, there is a need to pass data between processing elements. In many instances when multiple processing elements are working together to perform a given task, it is desirable to improve parallelism where possible to decrease overall execution time. An upstream processing element performs a fork operation to provide data to multiple downstream processing elements. The processing elements within the reconfigurable fabric are controlled by circular buffers. The circular buffers are statically scheduled. The fork operation provides for computation to be divided amongst multiple processing elements. An efficient forking mechanism is a key component in achieving optimal performance of a multiple processing element system.

Abstract: Disclosed embodiments provide techniques for data manipulation with logic circuitry. One or more processing elements are reconfigured in a connected topology. The reconfiguring enables the implementation of a dataflow graph. A FIFO is dynamically configured between a pair of neighboring processing elements. The FIFO contains data and/or instructions for processing elements. A process agent executing on the processing element coordinates transfer of data to/from FIFOs and processing elements. The processing elements are controlled by circular buffers. The circular buffers are statically scheduled. Processing elements enter and exit a sleep mode based on data conditions of the interconnected FIFOs. The FIFOs are configured to minimize adverse effects of latency, while process agents issue and receive signals to enable synchronization between processing elements.

Abstract: Techniques are disclosed for data manipulation. Data is obtained from a first switching element where the first switching element is controlled by a first circular buffer. Data is sent to a second switching element where the second switching element is controlled by a second circular buffer. Data is controlled by a third switching element that is controlled by a third circular buffer. The third switching element hierarchically controls the first switching element and the second switching element. Data is routed through a fourth switching element that is controlled by a fourth circular buffer. The circular buffers are statically scheduled. The obtaining data from a first switching element and the sending the data to a second switching element includes a direct memory access (DMA). The switching elements can operate as a master controller or as a slave device. The switching elements can comprise clusters within an asynchronous reconfigurable fabric.

Abstract: Techniques are disclosed for data manipulation. A memory request is initiated from a first cluster within a reconfigurable fabric. The memory request is queued within a first FIFO for execution by an external memory direct memory access (DMA) master. The memory request is issued to an external memory. The external memory is associated with the external memory DMA master. The external memory is accessed based on the memory request. Data is transferred between the external memory and a second cluster within the reconfigurable fabric, facilitated by a second FIFO. The queuing is accomplished by a queue manager, the first FIFO, and the second FIFO. The first FIFO and the second FIFO are controlled by circular buffers. A read clock for the first FIFO is based on a clock for the first FIFO's circular buffer, whereas a write clock is based on a clock for the external memory.

Abstract: A combination of memory units and dataflow processing units is disclosed for computation. A first memory unit is interposed between a first dataflow processing unit and a second dataflow processing unit. Operations for a dataflow graph are allocated across the first dataflow processing unit and the second dataflow processing unit. The first memory unit passes data between the first dataflow processing unit and the second dataflow processing unit to execute the dataflow graph. The first memory unit is a high bandwidth, shared memory device including a hybrid memory cube. The first dataflow processing unit and second dataflow processing unit include a plurality of circular buffers containing instructions for controlling data transfer between the first dataflow processing unit and second dataflow processing unit. Additional dataflow processing units and additional memory units are included for additional functionality and efficiency.

Abstract: Techniques are disclosed for power conservation. A plurality of processing elements and a plurality of instructions are configured. The plurality of processing elements is controlled by instructions contained in a plurality of circular buffers. The plurality of processing elements can comprise a dataflow processor. A first processing element, from the plurality of interconnected processing elements, is set into a sleep state by a first instruction from the plurality of instructions. The first processing element is woken from the sleep state as a result of valid data being presented to the first processing element. A subsection of the plurality of interconnected processing elements is also set into a sleep state based on the first processing element being set into a sleep state.

Abstract: Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions for the implementation of multiple functions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.

Abstract: A plurality of software programmable processors is disclosed. The software programmable processors are controlled by rotating circular buffers. A first processor and a second processor within the plurality of software programmable processors are individually programmable. The first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors. The first processor sends and receives data from the neighbor processors. The first processor and the second processor are configured to operate on a common instruction cycle. An output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle.

Abstract: Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.

Abstract: A processing device is provided. A cluster includes a plurality of groups of processing elements. A multi-word device is connected to the processing elements within the groups. Each processing element in a particular group is in communication with all other processing elements within the particular group, and only one of the processing elements within other groups in the cluster. Each processing element is limited to operations in which input bits can be processed and an output obtained without reference to other bits. The multi-word device is configured to cooperate with at least two other processing elements to perform processing that requires reference to other bits to obtain a result.

Abstract: Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is swapped to storage. Data stored in circular buffers is paged in and out to a second level memory. State information for each logical element is also saved and restored using paging memory. Logical elements such as processing elements are provided instructions via circular buffers. The instructions enable a group of processing elements to perform operations implementing a desired functionality. That functionality is changed by updating the circular buffers with new instructions that are transferred from paging memory. The previous instructions can be saved off in paging memory before the new instructions are copied over to the circular buffers. This enables the hardware to be rapidly reconfigured amongst multiple functions.