Abstract: An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. In accordance with an illustrative embodiment of the invention, the prefix trees are interconnected such that carry signals are computed at least partially in parallel. For example, a carry signal computed in an initial stage of a given prefix tree is used in subsequent stages of the given prefix tree without introducing substantial additional delay in computation of other carry signals in other prefix trees associated with higher bit positions. Carries computed for lower bit positions are thus used to compute carries for higher bit positions, but generate, propagate and/or transmit signals may be generated in an initial stage of each of the prefix trees without utilizing a primary carry input signal in the computation. The resulting adder architecture provides reduced logic depth, delay and circuit area relative to conventional architectures.

Abstract: A cache implements bank-by-bank locking to keep critical code from being flushed out of the cache. A register is maintained to rank the banks from the most recently used to the least recently used. Ordinarily, when code needs to be moved into the cache, the least recently used bank is flushed, the code is moved into that bank, and the register is updated to identify that bank as the most recently used. However, if a bank is designated in a bypass vector as being locked, that bank is bypassed in the maintenance of the register and is thus never identified as the bank to be flushed.

Abstract: Multiported register files are employed to implement the input delays necessary for finite impulse response (FIR) filter operation. A multiported register file is a memory, typically small, with at least one read port and one write port. Data written into the multiported register file may be read out therefrom in any desired order. The multiported register tile may have additional output ports from which the data stored therein may be read out, also in any desired order, and independent from the order of any other output port. At least one output of each multiported register file is coupled to the input of the next stage of the FIR filter, if any. In addition, each multiported register file feeds data from one output to the multiply-add portion of its associated stage of the FIR filter.

Abstract: Power consumption in program implemented circuits and the like is dynamically controlled in accordance with the circuit performance over time, not by reducing switched capacitance as was done in prior hardware circuit implementations but, in accordance with the invention, by dynamically reducing the number of machine cycles required to implement the desired circuit at an acceptable performance level. Power consumption is dynamically reduced in program implemented circuits, for example, circuits implemented on a digital signal processor (DSP), including filters employed for channel equalization and for echo cancellation by monitoring the circuit performance over time and dynamically scaling back filter parameters when less than worst case performance is required.

Abstract: The NEG output of the Booth encoding circuit and the multiplicand input are gated so as to minimize switching activity in the multiplier without adding any delay to the critical path thereof. Advantageously, power consumption in the multiplier is significantly reduced, e.g., on the order of 90%, when multiplication is in fact not being performed. Additionally, by changing the structure of the last XOR gate of the partial product generation circuit, the need to gate the multiplicand input can be eliminated. Advantageously, this eliminates the extra circuitry which would otherwise be required to gate the multiplicand input, thus reducing cost. Furthermore, additional power savings may be achieved by efficiently resynchronizing the multiplicand input with the Booth encoded input to the partial product circuit.

Abstract: A method and system for determining a route for a packet traveling over at least one system from a source to a destination is disclosed. A first geographic area corresponds to the source and a second geographic area corresponds to the destination. The destination further has an address which does not indicate the second geographic area. In this aspect, the method and system include associating an address for the destination with the second geographic area to allow selection of the route for the data packet based on the second geographic area and selecting the route based on a second geographic area. In a second aspect, the method and system include providing a direct link having a controllable amount of traffic and selecting the direct link as at least a portion of the route when a data packet to the destination is to be routed. The method and system also facilitate selection of a route for a data packet. In this aspect, the method and system include obtaining information relating to an autonomous system.

Abstract: The NEG output of the Booth encoding circuit and the multiplicand input are gated so as to minimize switching activity in the multiplier without adding any delay to the critical path thereof. Advantageously, power consumption in the multiplier is significantly reduced, e.g., on the order of 90%, when multiplication is in fact not being performed. Additionally, by changing the structure of the last XOR gate of the partial product generation circuit, the need to gate the multiplicand input can be eliminated. Advantageously, this eliminates the extra circuitry which would otherwise be required to gate the multiplicand input, thus reducing cost. Furthermore, additional power savings may be achieved by efficiently resynchronizing the multiplicand input with the Booth encoded input to the partial product circuit.

Abstract: In a digital filter having tap coefficients, a gain element is employed to scale the filter output. The gain element is controlled by an error monitor element which runs an adaptive process in accordance with the invention. Such a process causes each tap coefficient value to be changed so as to reduce power consumption in the filter. On the other hand, the process ensures that the filter output maintains an acceptable signal to noise ratio (SNR), despite losing the bit precision of the filter as a result of the change of the coefficient values.

Abstract: A bicycle frame of relatively large diameter tubing formed of a light weight, high strength metal tubing, such as titanium, is provided with integral stiffeners at the top of the seat tube, the bottom of the down tube and the top of the fork blades. In larger sizes of frames, stiffeners may also be included at the bottom of the seat tube and at the top of the down tube. The placement of stiffeners at these selected locations results in overall frame stiffness characteristics not previously considered achievable without substantial increase in the weight of the frame. As an additional feature, the enlarged diameter of the down tube is reduced at appropriate locations to enable standard gear shift lever and control cable fittings to be used.