Patents by Inventor John Paul Strachan
John Paul Strachan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240153555Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Inventors: Catherine Graves, Giacomo Pedretti, Sergey Serebryakov, John Paul Strachan
-
Publication number: 20240112029Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.Type: ApplicationFiled: December 5, 2023Publication date: April 4, 2024Inventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, John Paul Strachan, Sergey Serebryakov
-
Publication number: 20240111970Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.Type: ApplicationFiled: December 4, 2023Publication date: April 4, 2024Inventors: John Paul Strachan, Dejan S. Milojicic, Martin Foltin, Sai Rahul Chalamalasetti, Amit S. Sharma
-
Patent number: 11899965Abstract: A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.Type: GrantFiled: March 10, 2022Date of Patent: February 13, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Giacomo Pedretti, John Paul Strachan, Thomas Maurits M. Van Vaerenbergh, Catherine E. Graves
-
Publication number: 20240047002Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.Type: ApplicationFiled: October 9, 2023Publication date: February 8, 2024Inventors: Giacomo Pedretti, John Paul Strachan, Catherine Graves
-
Publication number: 20240046988Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learning memory. The analog output of the differentiable CAM can provide input to a learning algorithm, which may compute the gradients in comparison to historic values and reduce data inaccuracies and power consumption.Type: ApplicationFiled: July 28, 2022Publication date: February 8, 2024Inventors: GIACOMO PEDRETTI, Catherine GRAVES, Sergey SEREBRYAKOV, John Paul STRACHAN
-
Publication number: 20240039562Abstract: An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.Type: ApplicationFiled: October 9, 2023Publication date: February 1, 2024Inventors: John Paul Strachan, Catherine Graves, Can Li
-
Patent number: 11881261Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.Type: GrantFiled: December 17, 2021Date of Patent: January 23, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Catherine Graves, Giacomo Pedretti, Sergey Serebryakov, John Paul Strachan
-
Patent number: 11861429Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.Type: GrantFiled: April 30, 2018Date of Patent: January 2, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: John Paul Strachan, Dejan S. Milojicic, Martin Foltin, Sai Rahul Chalamalasetti, Amit S. Sharma
-
Patent number: 11853846Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.Type: GrantFiled: April 30, 2018Date of Patent: December 26, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, John Paul Strachan, Sergey Serebryakov
-
Patent number: 11804859Abstract: An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.Type: GrantFiled: January 20, 2022Date of Patent: October 31, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: John Paul Strachan, Can Li, Catherine Graves
-
Patent number: 11783907Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.Type: GrantFiled: October 29, 2021Date of Patent: October 10, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Giacomo Pedretti, John Paul Strachan, Catherine Graves
-
Publication number: 20230307048Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.Type: ApplicationFiled: May 31, 2023Publication date: September 28, 2023Inventors: Can Li, Catherine Graves, John Paul Strachan
-
Publication number: 20230289090Abstract: A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: Giacomo Pedretti, John Paul Strachan, Thomas Maurits M. Van Vaerenbergh, Catherine E. Graves
-
Patent number: 11735281Abstract: An analog content addressable memory (aCAM) that enables parallel searching of analog ranges of values and generates analog outputs that quantify matches between input data and stored data is disclosed. The input data can be compared with the stored data, and the input data can be determined to match the stored data based on a value associated with the input data being within a range associated with the stored data. The aCAM can generate an analog output that represents a number of matches and a number of mismatches between the input data and the stored data. Based on the analog output, whether the input data matches the stored data and a degree to which the input data matches the stored data can be determined.Type: GrantFiled: April 30, 2021Date of Patent: August 22, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Catherine Graves, Can Li, John Paul Strachan
-
Publication number: 20230246655Abstract: An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other nonvolatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.Type: ApplicationFiled: January 20, 2022Publication date: August 3, 2023Inventors: JOHN PAUL STRACHAN, CAN LI, CATHERINE GRAVES
-
Patent number: 11694749Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.Type: GrantFiled: May 3, 2021Date of Patent: July 4, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Can Li, Catherine Graves, John Paul Strachan
-
Publication number: 20230197151Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: CATHERINE GRAVES, GIACOMO PEDRETTI, SERGEY SEREBRYAKOV, JOHN PAUL STRACHAN
-
Patent number: 11650751Abstract: A method for determining a solution to a constrained optimization problem includes programming a weights matrix of a Hopfield network with a first encoded matrix representation of an initial constrained optimization problem. The method also includes employing the Hopfield network to determine a solution to the initial constrained optimization problem. Additionally, the method includes encoding a plurality of constrained optimization problems associated with a target constrained optimization problem into a plurality of encoded matrix representations each of which are a combination of the first and the second encoded matrix representations. The plurality of encoded matrix representations increases in convergence to the second encoded matrix representation of the target constrained optimization problem sequentially. The method further includes re-programming the weights matrix of the Hopfield network in an iterative manner with the plurality of encoded matrix representations.Type: GrantFiled: March 29, 2019Date of Patent: May 16, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Suhas Kumar, Thomas Van Vaerenbergh, John Paul Strachan
-
Patent number: 11650953Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.Type: GrantFiled: October 16, 2020Date of Patent: May 16, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan