Patents by Inventor John Purcell

John Purcell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240095259
    Abstract: Systems and methods are provided for storing a first data object comprising a first set of immutable components, the first data object being associated with a corresponding second data object stored by a remote replication system. A difference is determined between the first set of immutable components of the first data object and a second set of immutable components of the corresponding second data object. A subset of immutable components is identified from the first set of immutable components based on the difference. The subset of immutable components from the first set of immutable components is provided to the remote replication system over a communication network.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Stephen Freiberg, Alexander Landau, Andrew Greene, Brian Dorne, Bryan Offutt, Ernest Zeidman, Ilya Nepomnyaschchiy, John Garrod, Katherine Brainard, Kolin Purcell, Michael Levin, Simon Swanson, Spencer Stecko
  • Patent number: 11918200
    Abstract: Meniscal extrusion can occur due detachment of the knee capsule from structures of the knee. Disclosed herein are methods to repair the meniscal detachment. Additionally, cadaveric and synthetic models can be used to teach said methods of repair.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 5, 2024
    Assignee: Arthrex, Inc.
    Inventors: David Crane, George Paletta, John Purcell, Andrew Osika, Robert Harrison
  • Patent number: 11893423
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 6, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Sonata Gale Wen, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Publication number: 20230316186
    Abstract: The disclosure is directed to various ways of improving the functioning of computer systems, information networks, data stores, search engine systems and methods, and other advantages. Among other things, provided herein are methods, systems, components, processes, modules, blocks, circuits, sub-systems, articles, and other elements (collectively referred to in some cases as the “platform” or the “system”) that collectively enable, in one or more datastores (e.g., where each datastore may include one or more databases) and systems, the creation, development, maintenance, and use of a set of custom objects for use in a wide range of activities, including sales activities, marketing activities, service activities, content development activities, and others, as well as improved methods and systems for sales, marketing and services that make use of such entity resolution systems and methods as well as custom objects.
    Type: Application
    Filed: June 9, 2023
    Publication date: October 5, 2023
    Inventors: Joshua James MILLER, Marco Lagi, Stephen John Purcell, Stuart Pope Layton, Jared Michael Williams, Bryan Frederick Ash, Sophie Alice Higgs, Robert Fletcher McEneaney, Dyan Christopher Sellberg, Anna Coffey, Hector Urdiales, Edward Forbes Burns, II
  • Patent number: 11704962
    Abstract: The present invention discloses a gaming apparatus comprising: a digital screen display mounted on a support, an actuation mechanism arranged for moving the digital screen display around an axis of rotation, at least one position identification member, a position sensing mechanism arranged for at least detecting the position of the prize segments with respect to the at least one position identification member; and a computer system. The computer system arranged for transmitting the electronic prize game digital image and associated prize information for display on the digital screen display, and for detecting, based on the position information obtained from the position sensing mechanism, at least one prize segment associated with the at least one stopping position of the digital display screen.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: July 18, 2023
    Inventor: John Purcell
  • Patent number: 11663036
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 30, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Eric Rock, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Patent number: 11635986
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 25, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Eric Rock, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Patent number: 11579925
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 14, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Eric Rock, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Patent number: 11249905
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 15, 2022
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Eric Rock, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Publication number: 20210290220
    Abstract: Meniscal extrusion can occur due detachment of the knee capsule from structures of the knee. Disclosed herein are methods to repair the meniscal detachment. Additionally, cadaveric and synthetic models can be used to teach said methods of repair.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Applicant: ARTHREX, INC.
    Inventors: David CRANE, George PALETTA, John PURCELL, Andrew OSIKA, Robert HARRISON
  • Patent number: 11058408
    Abstract: Meniscal extrusion can occur due detachment of the knee capsule from structures of the knee. Disclosed herein are methods to repair the meniscal detachment. Additionally, cadaveric and synthetic models can be used to teach said methods of repair.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 13, 2021
    Assignee: ARTHREX, INC.
    Inventors: David Crane, George Paletta, John Purcell, Andrew Osika, Robert Harrison
  • Publication number: 20210157651
    Abstract: A parallel processing unit (PPU), operating in a traditional processing environment or in a virtualized processing environment, can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Inventors: Jerome F. DULUK, Jr., Gregory Scott PALMER, Jonathon Stuart Ramsay EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL
  • Publication number: 20210082236
    Abstract: The present invention discloses a gaming apparatus comprising: a digital screen display mounted on a support, an actuation mechanism arranged for moving the digital screen display around an axis of rotation, at least one position identification member, a position sensing mechanism arranged for at least detecting the position of the prize segments with respect to the at least one position identification member; and a computer system. The computer system arranged for transmitting the electronic prize game digital image and associated prize information for display on the digital screen display, and for detecting, based on the position information obtained from the position sensing mechanism, at least one prize segment associated with the at least one stopping position of the digital display screen.
    Type: Application
    Filed: April 9, 2019
    Publication date: March 18, 2021
    Inventor: John Purcell
  • Publication number: 20210073042
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Jerome F. DULUK, Jr., Gregory Scott PALMER, Jonathon Stuart Ramsey EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL
  • Publication number: 20210073125
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Jerome F. DULUK, JR., Gregory Scott PALMER, Jonathon Stuart Ramsey EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL
  • Publication number: 20210073025
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Jerome F. DULUK, JR., Gregory Scott PALMER, Jonathon Stuart Ramsey EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL
  • Publication number: 20210073035
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Jerome F. DULUK, Jr., Gregory Scott PALMER, Jonathon Stuart Ramsey EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL
  • Publication number: 20200140529
    Abstract: The present invention provides methods and compositions useful in the field of medicine, and particularly in the treatment of viral infections. More particularly, the invention relates to the use of methods and compositions for the inhibition of human immunodeficiency virus (HIV) transmission.
    Type: Application
    Filed: November 1, 2019
    Publication date: May 7, 2020
    Inventor: Damian Francis John Purcell
  • Publication number: 20190330167
    Abstract: The present invention relates to novel compounds which active HIV expression in latently infected cells. More particularly, the invention relates to pharmaceutical compositions comprising the novel compounds and their use in activating HIV expression in latently infected cells. Further still, the invention relates to pharmaceutical compositions comprising the novel compounds in combination with anti-HIV therapy compounds and their use in treating HIV infection in both animals and humans. The invention further provides means for preparing the compounds.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 31, 2019
    Inventors: Brad SLEEBS, Damian Francis John PURCELL, Jonathan JACOBSON, Sharon LEWIN, William NGUYEN
  • Patent number: 10310973
    Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: June 4, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Nick Barrow-Williams, Brian Fahs, Jerome F. Duluk, Jr., James Leroy Deming, Timothy John Purcell, Lucien Dunning, Mark Hairgrove