Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

Abstract: Meniscal extrusion can occur due detachment of the knee capsule from structures of the knee. Disclosed herein are methods to repair the meniscal detachment. Additionally, cadaveric and synthetic models can be used to teach said methods of repair.

Abstract: Meniscal extrusion can occur due detachment of the knee capsule from structures of the knee. Disclosed herein are methods to repair the meniscal detachment. Additionally, cadaveric and synthetic models can be used to teach said methods of repair.

Abstract: Meniscal extrusion can occur due detachment of the knee capsule from structures of the knee. Disclosed herein are methods to repair the meniscal detachment. Additionally, cadaveric and synthetic models can be used to teach said methods of repair.

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

Abstract: The present invention provides methods and compositions useful in the field of medicine, and particularly in the treatment of viral infections. More particularly, the invention relates to the use of methods and compositions for the inhibition of human immunodeficiency virus (HIV) transmission.

Abstract: One embodiment of the present invention sets forth a technique for error-checking a compute task. The technique involves receiving a pointer to a compute task, storing the pointer in a scheduling queue, determining that the compute task should be executed, retrieving the pointer from the scheduling queue, determining via an error-check procedure that the compute task is eligible for execution, and executing the compute task.

Abstract: The present invention provides methods for transforming monocot plants via a simple and rapid protocol, to obtain regenerated plants capable of being planted to soil in as little as 4-8 weeks. Associated cell culture media and growth conditions are also provided, as well as plants and plant parts obtained by the method. Further, a method for screening recalcitrant plant genotypes for transformability by the methods of the present invention is also provided. Further, a system for expanding priority development window for producing transgenic plants by the methods of the present invention is also provided.

Abstract: Meniscal extrusion can occur due detachment of the knee capsule from structures of the knee. Disclosed herein are methods to repair the meniscal detachment. Additionally, cadaveric and synthetic models can be used to teach said methods of repair.

Abstract: Meniscal extrusion can occur due detachment of the knee capsule from structures of the knee. Disclosed herein are methods to repair the meniscal detachment. Additionally, cadaveric and synthetic models can be used to teach said methods of repair.

Abstract: The present invention provides methods for transforming monocot plants via a simple and rapid protocol, to obtain regenerated plants capable of being planted to soil in as little as 4-8 weeks. Associated cell culture media and growth conditions are also provided, as well as plants and plant parts obtained by the method. Further, a method for screening recalcitrant plant genotypes for transformability by the methods of the present invention is also provided. Further, a system for expanding priority development window for producing transgenic plants by the methods of the present invention is also provided.

Abstract: One embodiment of the present invention sets forth a technique for selecting a first processor included in a plurality of processors to receive work related to a compute task. The technique involves analyzing state data of each processor in the plurality of processors to identify one or more processors that have already been assigned one compute task and are eligible to receive work related to the one compute task, receiving, from each of the one or more processors identified as eligible, an availability value that indicates the capacity of the processor to receive new work, selecting a first processor to receive work related to the one compute task based on the availability values received from the one or more processors, and issuing, to the first processor via a cooperative thread array (CTA), the work related to the one compute task.

Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty.

Abstract: One embodiment of the present invention sets forth a technique for managing the allocation and release of resources during multi-threaded program execution. Programmable reference counters are initialized to values that limit the amount of resources for allocation to tasks that share the same reference counter. Resource parameters are specified for each task to define the amount of resources allocated for consumption by each array of execution threads that is launched to execute the task. The resource parameters also specify the behavior of the array for acquiring and releasing resources. Finally, during execution of each thread in the array, an exit instruction may be configured to override the release of the resources that were allocated to the array. The resources may then be retained for use by a child task that is generated during execution of a thread.

Abstract: One embodiment of the present invention sets forth a technique for computing line stipple using a parallel rasterizer. Stipple phases are computed in parallel for individual line segments of a line strip during the viewport scale, cull, and clipping operations. The line segments are distributed to multiple parallel rasterizers. Each line segment may be sent to only one of the parallel rasterizers. Update phase messages that include an accumulated stipple phase for a batch of line segments are broadcast to all of the multiple parallel rasterizers. The update phase messages are used by the multiple parallel rasterizers to reconstruct the stipple phases for each line segment of a line strip in order to correctly render stippled line strips and produce a continuous stippled line.

Abstract: Techniques described herein generally relate to extended supply chain management. In an embodiment, extended supply chains may be evaluated and managed by efficiently linking current, past, and/or upcoming consumer demand signals to the supply chain. The extended supply chains may be managed at select points along the extended supply chains and at select points in time. Other embodiments are disclosed and claimed.

Abstract: Disclosed herein is an internal combustion engine includes a cylinder with a mid-stop shelf and a liner positioned within the cylinder. The liner includes a seat supported on the mid-stop shelf. Further, the liner defines a piston channel. The engine also includes a coolant conduit between the cylinder and the liner. The coolant conduit located above the mid-stop shelf and seat. Additionally, the engine includes a piston with a head portion and a skirt portion. The piston is movable within the piston channel between an upper-most position and a lowermost position. In the upper-most position, the skirt portion of the piston is positioned below the mid-stop shelf and seat.

Abstract: One embodiment of the present invention sets forth a technique for assigning a compute task to a first processor included in a plurality of processors. The technique involves analyzing each compute task in a plurality of compute tasks to identify one or more compute tasks that are eligible for assignment to the first processor, where each compute task is listed in a first table and is associated with a priority value and an allocation order that indicates relative time at which the compute task was added to the first table. The technique further involves selecting a first task compute from the identified one or more compute tasks based on at least one of the priority value and the allocation order, and assigning the first compute task to the first processor for execution.

Abstract: One embodiment of the present invention sets forth a technique for enabling the insertion of generated tasks into a scheduling pipeline of a multiple processor system allows a compute task that is being executed to dynamically generate a dynamic task and notify a scheduling unit of the multiple processor system without intervention by a CPU. A reflected notification signal is generated in response to a write request when data for the dynamic task is written to a queue. Additional reflected notification signals are generated for other events that occur during execution of a compute task, e.g., to invalidate cache entries storing data for the compute task and to enable scheduling of another compute task.

Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.