Abstract: A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.

Abstract: A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.

Abstract: A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.

Abstract: A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.

Abstract: A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.

Abstract: A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.

Abstract: A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.

Abstract: A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.

Abstract: A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.

Abstract: In one exemplary embodiment, the disclosed VLIW processor comprises a number of threads where each thread includes a processing unit. For example, there can be two threads, where each of the two threads has its own processing unit. According to this exemplary embodiment, a number of VLIW packets are divided into a number of issue groups. As an example, two VLIW packets are divided into two issue groups each. The first issue group in the first VLIW packet is provided to a first thread for execution in the first thread processing unit during a first clock cycle. Concurrently, the first issue group in the second VLIW packet is provided to a second thread for execution in the second thread processing unit during the same clock cycle, i.e. during the first clock cycle. Moreover, the second issue group in the first VLIW packet is provided to the first thread for execution in the first thread processing unit during a second clock cycle.

Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

Abstract: A low power instruction cache is disclosed. There are a number of tag memory banks. Each tag memory bank is associated with a unique instruction cache. Each tag memory bank has a number of tag memory rows and each tag memory row has a number of tag memory cells. Certain upper bits of a program counter are compared to a tag stored in one row of a tag memory bank. If there is a match between the certain upper bits of the program counter and the tag, a hit signal is generated. The hit signal indicates that the tag memory bank containing the matched row (i.e. the matched tag) is associated with the instruction cache having a desired instruction. The desired instruction is then read from the instruction cache associated with the tag memory bank corresponding to the generated hit signal. Thus, instead of reading one instruction from each of the instruction caches and then eliminating all but one of the read instructions, only the desired instruction from a single instruction cache is read.

Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

Abstract: In one exemplary embodiment, the disclosed VLIW processor comprises a number of threads where each thread includes a processing unit. For example, there can be two threads, where each of the two threads has its own processing unit. According to this exemplary embodiment, a number of VLIW packets are divided into a number of issue groups. As an example, two VLIW packets are divided into two issue groups each. The first issue group in the first VLIW packet is provided to a first thread for execution in the first thread processing unit during a first clock cycle. Concurrently, the first issue group in the second VLIW packet is provided to a second thread for execution in the second thread processing unit during the same clock cycle, i.e. during the first clock cycle. Moreover, the second issue group in the first VLIW packet is provided to the first thread for execution in the first thread processing unit during a second clock cycle.

Abstract: A method of remote loading of confidential information between a secure pin entry device and a Authorzing Institute using public and private key encryption techniques. In addition, a digital certificate uniquely identifying the terminal is provided by the terminal when a communication with the Authorzing Institute is originated. The Authorzing Institute confirms the authenticity of the digital certificate. This confirmation can occur using the public key of the Certificate Authority and/or confirmation can be made by contacting the Certificate Authority. In this way, confidence to use the public and private keys of the device and the Authorizing Institute for encryption is achieved, and financial keys and/or software can be encrypted downloaded to the device.

Abstract: The present invention provides an efficient method of forwarding and sharing information between functional units and register files in an effort to execute instructions. A digital signal processor includes a plurality of register blocks for storing data operands coupled to a plurality of data path units for executing instructions. Preferably, each register block is coupled to at least two data path units. In addition, the processor preferably has a plurality of forwarding paths which forward information from one data path unit to another. A scheduler efficiently forwards instructions to data path units based on information regarding the configuration of the processor and any restrictions which might be imposed on the scheduler.

Abstract: The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred embodiment of the invention where the supply voltage is 3.0 volts, the two NFET transistors result in a voltage drop of 2.0 volts so as to produce a reference precharge signal or a bit line precharge signal having a voltage of 1.0 volts. When a precharge enable signal is on, the PFET transistor is connected to ground and is barely on such that the path from the reference precharge signal or the bit line precharge signal to ground is a low impedance path. Moreover, the path from the reference precharge signal or the bit line precharge signal to the supply voltage is also of low impedance. Accordingly, the voltages present at the reference precharge signal or the bit line precharge signal are substantially noise free.

Abstract: The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred embodiment of the invention where the supply voltage is 3.0 volts, the two NFET transistors result in a voltage drop of 2.0 volts so as to produce a reference precharge signal or a bit line precharge signal having a voltage of 1.0 volts. When a precharge enable signal is on, the PFET transistor is connected to ground and is barely on such that the path from the reference precharge signal or the bit line precharge signal to ground is a low impedance path. Moreover, the path from the reference precharge signal or the bit line precharge signal to the supply voltage is also of low impedance. Accordingly, the voltages present at the reference precharge signal or the bit line precharge signal are substantially noise free.

Abstract: The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred embodiment of the invention where the supply voltage is 3.0 volts, the two NFET transistors result in a voltage drop of 2.0 volts so as to produce a reference precharge signal or a bit line precharge signal having a voltage of 1.0 volts. When a precharge enable signal is on, the PFET transistor is connected to ground and is barely on such that the path from the reference precharge signal or the bit line precharge signal to ground is a low impedance path. Moreover, the path from the reference precharge signal or the bit line precharge signal to the supply voltage is also of low impedance. Accordingly, the voltages present at the reference precharge signal or the bit line precharge signal are substantially noise free.