Abstract: A high speed current sense amplifier useful in memory devices, which includes a current-to-voltage amplifier that is coupled to a voltage amplifier. The current-to-voltage amplifier has an input impedance that is lower than its output impedance. The voltage amplifier has an input impedance that is larger than the input impedance of the current-to-voltage amplifier. The current sense amplifier can sense the current relationship between two current inputs in about 200 pico-seconds. Embodiments of the current sense amplifier enable current sensing either near the power supply voltage or near ground, thus eliminating the need for intermediate voltages. Embodiments of the current sense amplifier draw current from the current inputs only during the 200 pico-second sensing time and does not require external latching circuitry.

Abstract: A low voltage driver tolerant of high voltage and suitable for driving a processor and a memory device. A first protection NFET is coupled to the drains of a series-coupled PFET and NFET forming the basic driver components. Another protection NFET is connected in series to the first NFET. This second protection NFET requires approximately 1 volt for turn on, such that a resultant 3 volts appear at the output of the complete driver assembly. When the output driver is not enabled and 5 volt inputs are being applied from the memory circuit, the two NFET protection transistors block the 5 volts from reaching the processor output driver.

Abstract: An apparatus is disclosed for exercising a person's knee. The apparatus includes a base member that supports a person in a supine position. There are a pair of shoulder braces connected to and extending upwardly from the base member. Each shoulder brace engages a respective shoulder of the supported person. An elongate strap is interconnected to and extends between the shoulder braces. The strap extends across the back of the supported person's leg to hold the upper section of the leg, located generally above the knee, in an upright condition extending upwardly from the base member. The lower section of the leg, located generally below the knee, may be selectively lowered and raised relative to the upper section of the leg to stretch and strengthen the knee.

Abstract: The present invention is directed to game cards and systems for tracking game cards. A computer tracking system is used which includes game or lottery type cards which must be activated to be eligible for a particular game or event. The activation step includes reading of a unique serial number or other identification code uniquely identifying the card. With this system, surplus game cards can be disposed of when they have not been activated. This simplifies tracking of sales of game cards and simplifies the distribution of funds to various parties in the sale and distribution chain.

Abstract: The LOW POWER CRYSTAL OSCILLATOR shown here reduces power consumption of a Pierce oscillator which has an inverter preferably made of an NFET N0 and a PFET P0 in series. A load, preferably an NFET N1 with its gate wired to its source, is placed in parallel with a switch, preferably a PFET P1, between P0 and Vcc. A clamp, preferably a PFET P2 with its gate wired to its source, is placed in parallel with a switch, preferably an NFET N2, between N0 and ground. The switches are enabled during power-up, thereby providing quick turn-on of the oscillator. They are then disabled, thereby reducing the voltage across the crystal XTAL and consequently reducing the power consumed.

Abstract: An oscillator circuit provides a symmetrical signal without halving the frequency of a crystal oscillator 12. The input 14 of the crystal oscillator 12 is low pass filtered, and the output 18 of the filter 16 is differential voltage compared with the input 14 of the crystal oscillator 12. The output 22 of the differential voltage comparator 20 is symmetrical and of the same frequency as the crystal oscillator 12. The crystal oscillator 12 is preferably a Pierce oscillator.

Abstract: A simplified CMOS toggle flip-flop includes a flip-flop that has an input and an output, and a toggle circuit that includes an inverter having an input connected to the flip-flop output, a transfer switch connected between the inverter output and the flip-flop input, and a toggle control responsive to an input toggle signal for closing the transfer switch to connect the inverter output to the flip-flop input to transfer the inverted flip-flop output state to the flip-flop input. The transfer switch may include an NFET having its conduction path connected between the inverter output and the flip-flop input, and having a control gate. The toggle control may include a NAND gate having a first input for receiving a toggle pulse and a second input for receiving a timing pulse, and having an output. A second inverter has an input connected to the NAND gate output and an output connected to the NFET control gate of the transfer switch.

Abstract: A circuit for charging a capacitive load such as a data or address bus in a VLSI circuit includes a voltage source input, a PFET switch connected between the voltage source input and the capacitive load or bus, and a voltage regulator connected to the capacitive load and to the gate of the PFET switch to cause the switch to conduct during a predetermined time only if the voltage on the capacitive load is less than a predetermined voltage, and to disconnect the capacitive load from the voltage source input when the voltage on the capacitive load reaches or exceeds that predetermined voltage level. The voltage regulator may include a first inverter having its input connected to the bus and a second inverter having an input connected to the output of the first inverter and having an output connected to the control input of the switch. The first inverter is constructed to output a low level when the voltage on the first inverter input is at or above the designated predetermined voltage.

Abstract: A non-volatile memory cell circuit for storing and recalling a digital signal, the memory cell circuit having a store cycle having a repeating series of recurring store cycle sequences; each store cycle sequence being controlled by an HIV Signal and a STORE SIGNAL. The memory cell circuit also has a recall cycle controlled by a MEMORY RESET SIGNAL to preset the state of the memory cell circuit during a first interval, a RECALL OUTPUT CONTROL SIGNAL and a RECALL TRANSFER SIGNAL in a second reset signal interval. The memory cell has a VOLATILE RAM CELL with a flip-flop having first and second nodes at which complementary output signals are provided. The flip-flop also has a SET TERMINAL responsive to a set signal for forcing the flip-flop to assume a predetermined state coupled to the first node and a RESET TERMINAL responsive to the RESET SIGNAL.

Abstract: A memory cell circuit for storing the state of a digital signal on a data bus in response to an address signal. The memory cell has a store cycle with a repeating series of recurring store cycle sequences, each store cycle sequence having a (HIV) high-voltage timing signal during a first interval, and first and second store timing signals. The memory cell circuit also has a recall cycle. Each recall cycle has a memory reset signal to pre-set the state of the memory cell circuit during a first interval, a recall output signal at a predetermined voltage level and a recall transfer signal. The memory cell comprises a volatile RAM cell having a flip-flop providing an output signal at an output terminal. The flip-flop also has a RESET TERMINAL responsive to a reset signal for forcing the flip-flop to assume a predetermined state in response to the memory reset signal and a SET TERMINAL responsive to a set signal for setting the state of the volatile RAM cell in a recall sequence.

Abstract: A random access memory cell includes a volatile RAM cell, a non-volatile RAM cell and a transfer control circuit connected between the volatile and non-volatile elements. The volatile element includes two nodes and has two stable states. The non-volatile element also includes two nodes, each of which is connected to one of the nodes of the volatile element. The non-volatile element preferably includes a floating gate field effect transistor used as a storage transistor and connected between the two nodes of the non-volatile element to store a charge corresponding to the state of the non-volatile element. A second floating gate field effect transistor is coupled to the storage transistor to be used as a sense transistor. The transfer control circuit selectively connects the sense transistor to one of the nodes of the volatile element to cause the volatile element to adopt the state represented by the charge on the storage transistor of the non-volatile element.

Abstract: A semiconductor circuit and method for comparing an input signal voltage level against the circuit's supply voltage level and for providing a corresponding binary output signal, the circuit comprising first and second semiconductor devices for establishing voltage levels corresponding to the compared voltage levels on first and second nodes, respectively, third, fourth, fifth, and sixth semiconductor devices in combination with third, fourth, and fifth nodes arranged and connected to operate as a bistable element which is predisposed during a first time interval to favor one of the binary states in response to the difference in voltage levels established on the first and second nodes, and through the action of a seventh semiconductor device, which switches the main conductive path through the circuit off during the first interval and on during a second time interval, effecting a regenerative toggling of the bistable element to the favored state during the second time interval causing the desired binary signal

Abstract: A tri-state driver circuit is provided having a first clock node; and a second clock node, the first and second clock nodes being adapted to receive first and second clock signals from respectively first and second clock signal sources, the first clock signal being periodic and having a first and second logic level, the second clock signal being the complement of the first clock signal. A float node is included and is adapted to receive a complement float signal (F) having a first and second logic level from a float signal source, an array of input nodes are also included, each input node being adapted to receive an input signal having a first and second logic level from a respective input signal source. An array of output nodes are included, each output node corresponding to a respective input node and being coupled to a respective load.

Abstract: A low-power address decode logic circuit capable of and a method for decoding input address signals and for providing appropriate output address driver signals for retrieving selectively contents stored in memory. A first chargeable device connected to a first node is charged to provide that node with a logic high voltage level during the first of three successive time intervals, is allowed to remain charged or is discharged to provide a logic low voltage level on the first node in accordance with the decoded output of an input NOR gate which decodes the input address signals, while simultaneously gating to an output bootstrap driver a portion of the charge stored on the first chargeable device to cause a desired logic state voltage level to be stored in the driver during the second time interval, and using this logic state voltage level stored in the driver to bootstrap control the output address driver signal during the third time interval.

Abstract: An ac coupled, chopper stabilized differential comparator circuit characterized receiving a differential signal voltage applied between a signal input terminal and a reference signal input terminal, providing differential outputs at a first and second differential output terminal and being characterized as operating from a voltage source with respect to a reference potential comprising: amplifier means, characterized by a first stage differential amplifier having, a first channel amplifier having an input terminal and an output terminal. The first channel amplifier output terminal is connected to the first differential output terminal. The first stage differential amplifier also has a second channel amplifier having an input terminal and an output terminal. The second channel amplifier output terminal is connected to the second differential output terminal. The gain of the second channel amplifier is essentially equal to the gain of the first channel amplifier.

Abstract: A remotely located camera has a motor unit adjacent the camera-operating controls; namely, a shutter release button and a film advance lever. A ramp is mounted on a plate which is fixed to the motor shaft, with a film lever advance post also on the plate. Motor-reversing switches are located in circumferentially spaced positions about the plate, with the plate having switch actuators arranged to cause rotation of the plate to move the ramp to depress the button and release the film, then reverse the plate to move the post against the film lever to advance the film and then to again reverse the motor to bring the plate back to a home or start position.

Abstract: A voltage regulator circuit for reducing the noise sensitivity of digital logic circuits by controlling the voltage amplitude range of the clock signal.The circuit includes sensing means connected to the clock input for determining the range of the voltage amplitude of the input clock signal, a regulator circuit connected to the sensing circuit for limiting the voltage swing of the clock signal, and a clock output connected to the regulator circuit for supplying an output clock signal having a predetermined voltage amplitude range.

Abstract: A circuit having two modes of operation for driving either one of a light emitting diode or a gas discharge tube (digitron) display from a single semiconductor chip. Respective voltages are supplied to the chip to enable the circuit to selectively operate in either of the light emitting diode or digitron modes.

Abstract: A circuit having two modes of operation for driving either one of a light emitting diode or a gas discharge tube (digitron) display from a single semiconductor chip. Respective voltages are supplied to the chip to enable the circuit to selectively operate in either of the light emitting diode or digitron modes.