Patents by Inventor John R. Wilford
John R. Wilford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8902688Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.Type: GrantFiled: October 15, 2013Date of Patent: December 2, 2014Assignee: Micron Technology, Inc.Inventors: John Schreck, John R. Wilford
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Publication number: 20140043919Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.Type: ApplicationFiled: October 15, 2013Publication date: February 13, 2014Applicant: Micron Technology, Inc.Inventors: John Schreck, John R. Wilford
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Patent number: 8559259Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.Type: GrantFiled: February 29, 2012Date of Patent: October 15, 2013Assignee: Micron Technology, Inc.Inventors: John Schreck, John R. Wilford
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Publication number: 20120155201Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.Type: ApplicationFiled: February 29, 2012Publication date: June 21, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: John Schreck, John R. Wilford
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Patent number: 8130585Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.Type: GrantFiled: May 12, 2009Date of Patent: March 6, 2012Assignee: Micron Technology, Inc.Inventors: John Schreck, John R. Wilford
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Publication number: 20090225617Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.Type: ApplicationFiled: May 12, 2009Publication date: September 10, 2009Applicant: Micron Technology, Inc.Inventors: John Schreck, John R. Wilford
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Patent number: 7532532Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.Type: GrantFiled: May 31, 2005Date of Patent: May 12, 2009Assignee: Micron Technology, Inc.Inventors: John Schreck, John R. Wilford
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Patent number: 7050342Abstract: A method and apparatus for simultaneously accessing multiple array blocks in a static random access memory (SRAM) device. During testing of the SRAM device, each memory cell in each memory array block is accessed to ensure proper functionality. By providing logic gates on each SRAM device, the testing can be accelerated by writing to multiple array blocks at the same time, rather than in series.Type: GrantFiled: September 10, 2003Date of Patent: May 23, 2006Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, John R. Wilford
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Patent number: 6721233Abstract: An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.Type: GrantFiled: February 11, 2003Date of Patent: April 13, 2004Assignee: Micron Technology, Inc.Inventors: John R. Wilford, Joseph T. Pawlowski
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Publication number: 20040047226Abstract: A method and apparatus for simultaneously accessing multiple array blocks in a static random access memory (SRAM) device. During testing of the SRAM device, each memory cell in each memory array block is accessed to ensure proper functionality. By providing logic gates on each SRAM device, the testing can be accelerated by writing to multiple array blocks at the same time, rather than in series.Type: ApplicationFiled: September 10, 2003Publication date: March 11, 2004Inventors: Dean D. Gans, John R. Wilford
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Patent number: 6621755Abstract: A method and apparatus for simultaneously accessing multiple array blocks in a static random access memory (SRAM) device. During testing of the SRAM device, each memory cell in each memory array block is accessed to ensure proper functionality. By providing logic gates on each SRAM device, the testing can be accelerated by writing to multiple array blocks at the same time, rather than in series.Type: GrantFiled: August 30, 2001Date of Patent: September 16, 2003Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, John R. Wilford
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Publication number: 20030161206Abstract: An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.Type: ApplicationFiled: February 11, 2003Publication date: August 28, 2003Inventors: John R. Wilford, Joseph T. Pawlowski
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Patent number: 6570816Abstract: An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.Type: GrantFiled: October 21, 2002Date of Patent: May 27, 2003Assignee: Micron Technology, Inc.Inventors: John R. Wilford, Joseph T. Pawlowski
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Publication number: 20030048685Abstract: A method and apparatus for simultaneously accessing multiple array blocks in a static random access memory (SRAM) device. During testing of the SRAM device, each memory cell in each memory array block is accessed to ensure proper functionality. By providing logic gates on each SRAM device, the testing can be accelerated by writing to multiple array blocks at the same time, rather than in series.Type: ApplicationFiled: August 30, 2001Publication date: March 13, 2003Inventors: Dean D. Gans, John R. Wilford
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Publication number: 20030035339Abstract: An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.Type: ApplicationFiled: October 21, 2002Publication date: February 20, 2003Inventors: John R. Wilford, Joseph T. Pawlowski
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Patent number: 6469954Abstract: An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.Type: GrantFiled: August 21, 2000Date of Patent: October 22, 2002Assignee: Micron Technology, Inc.Inventors: John R. Wilford, Joseph T. Pawlowski
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Patent number: 6433403Abstract: A sacrificial conductive path formed in an integrated circuit to temporarily couple together semiconductor structures of the integrated circuit. The sacrificial conductive path includes a sacrificial area that severs the electrical continuity when it is removed. The sacrificial conductive path may be used to protect the gate oxide of a capacitive structure from charge related damage during a plasma etch step. The sacrificial structure temporarily couples the conductive layer of the capacitor structure to the substrate to discharge any charge accumulation. The sacrificial area will be removed prior to operation of the integrated device to sever the connection between the gate and the substrate. The sacrificial conductive path may be formed by an interconnect, and the sacrificial area removed by a plasma etch step. The sacrificial conductive path may also be formed by a semiconductor fuse having a sacrificial area that is removed by laser trimming.Type: GrantFiled: April 21, 1999Date of Patent: August 13, 2002Assignee: Micron Technology, Inc.Inventor: John R. Wilford
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Patent number: 6342723Abstract: A sacrificial conductive path formed in an integrated circuit to temporarily couple together semiconductor structures of the integrated circuit. The sacrificial conductive path includes a sacrificial area that severs the electrical continuity when it is removed. The sacrificial conductive path may be used to protect the gate oxide of a capacitive structure from charge related damage during a plasma etch step. The sacrificial structure temporarily couples the conductive layer of the capacitor structure to the substrate to discharge any charge accumulation. The sacrificial area will be removed prior to operation of the integrated device to sever the connection between the gate and the substrate. The sacrificial conductive path may be formed by an interconnect, and the sacrificial area removed by a plasma etch step. The sacrificial conductive path may also be formed by a semiconductor fuse having a sacrificial area that is removed by laser trimming.Type: GrantFiled: April 21, 1999Date of Patent: January 29, 2002Assignee: Micron Technology, Inc.Inventor: John R. Wilford
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Patent number: 6323076Abstract: A sacrificial conductive path formed in an integrated circuit to temporarily couple together semiconductor structures of the integrated circuit. The sacrificial conductive path includes a sacrificial area that severs the electrical continuity when it is removed. The sacrificial conductive path may be used to protect the gate oxide of a capacitive structure from charge related damage during a plasma etch step. The sacrificial structure temporarily couples the conductive layer of the capacitor structure to the substrate to discharge any charge accumulation. The sacrificial area will be removed prior to operation of the integrated device to sever the connection between the gate and the substrate. The sacrificial conductive path may be formed by an interconnect, and the sacrificial area removed by a plasma etch step. The sacrificial conductive path may also be formed by a semiconductor fuse having a sacrificial area that is removed by laser trimming.Type: GrantFiled: August 28, 2000Date of Patent: November 27, 2001Assignee: Micron Technology, Inc.Inventor: John R. Wilford
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Patent number: 6317381Abstract: A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the frequency of an externally applied clock signal. The memory device includes clock sensing circuitry that receives the clock signal and responsively produces a plurality of speed signals that transition a plurality of times corresponding in number to the frequency of the clock signal. The memory device also includes a control signal delay circuit that receives a memory command signal and the speed signals, and responsively produces a delayed control signal having a time delay from the command signal corresponding to the number of transitions of the speed signal value. Significantly, the control signal is generated during a period of the clock signal that immediately follows a period of the clock signal when the delay of the control signal delay circuit is set.Type: GrantFiled: December 7, 1999Date of Patent: November 13, 2001Assignee: Micron Technology, Inc.Inventors: Dean Gans, John R. Wilford, John D. Porter