Abstract: A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the externally applied system clock speed. The memory device includes clock sensing circuitry that receives the system clock signal and responsively produces a speed signal having a value corresponding to the frequency of the system clock signal. The clock sensing circuitry includes a plurality of series-connected time-delay circuits through which a signal derived from the system clock signal propagates. The clock sensing circuitry also includes a plurality of latch circuits, each coupled with a respective one of the time delay circuits and latching the value of the signal reaching the respective time delay circuit. The speed signal is then derived from these latched signal values, indicating through how many of the time-delay circuits the signal has propagated.

Abstract: A memory device is described which is operable in both a synchronous mode and a bus efficient mode (BE). Address and data register circuitry provide multiple propagation paths which can be selected based upon the operating mode and function performed. These features allow one memory device to be manufactured for multiple commercial applications. The address and data register circuitry have first and second paths, wherein the second paths are longer than the first paths. Control circuitry is provided to select the desired paths. During a synchronous and BE read operations, the first path of both the address and data register circuitry is selected. During BE write operations, the second path of the address register circuitry is selected. If the BE is operating in non-pipelined mode, the second path of the data register circuitry is selected.

Abstract: A signal translator circuit for particular use with low level logic signals is designed to accept a low level transitioning signal in a lower voltage range and output a signal transitioning within a higher voltage range. Circuitry is provided to ensure proper operation even at very low voltages. The circuitry which ensures proper operation at low voltages is selectively enabled when low input voltage input signals are used. In addition, the output signal is selectively disabled to allow downstream circuits to conserve energy during power up and power down cycles.

Abstract: A static random access memory device includes a plurality of local latch circuits coupled between a data communication line and a common memory array block. The local latch circuits allow a series of data signals to be received on the data communication line and latched for writing to the memory array block in one memory write operation. The local latch circuits provide for a burst of data to be written in a single memory array block in a single write operation.

Abstract: A memory device is described which is operable in both a synchronous mode and a bus efficient mode (BE). Address and data register circuitry provide multiple propagation paths which can be selected based upon the operating mode and function performed. These features allow one memory device to be manufactured for multiple commercial applications. The address and data register circuitry have first and second paths, wherein the second paths are longer than the first paths. Control circuitry is provided to select the desired paths. During a synchronous and BE read operations, the first path of both the address and data register circuitry is selected. During BE write operations, the second path of the address register circuitry is selected. If the BE is operating in non-pipelined mode, the second path of the data register circuitry is selected.

Abstract: A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the externally applied system clock speed. The memory device includes clock sensing circuitry that receives the system clock signal and responsively produces a speed signal having a value corresponding to the frequency of the system clock signal. The clock sensing circuitry includes a plurality of series-connected time-delay circuits through which a signal derived from the system clock signal propagates. The clock sensing circuitry also includes a plurality of latch circuits, each coupled with a respective one of the time delay circuits and latching the value of the signal reaching the respective time delay circuit. The speed signal is then derived from these latched signal values, indicating through how many of the time-delay circuits the signal has propagated.

Abstract: A signal translator circuit for particular use with low level logic signals is designed to accept a low level transitioning signal in a lower voltage range and output a signal transitioning within a higher voltage range. Circuitry is provided to ensure proper operation even at very low voltages. The circuitry which ensures proper operation at low voltages is selectively enabled when low input voltage input signals are used. In addition, the output signal is selectively disabled to allow downstream circuits to conserve energy during power up and power down cycles.

Abstract: A memory device is described which is operable in both a synchronous mode and a bus efficient mode (BE). Address and data register circuitry provide multiple propagation paths which can be selected based upon the operating mode and function performed. These features allow one memory device to be manufactured for multiple commercial applications. The address and data register circuitry have first and second paths, wherein the second paths are longer than the first paths. Control circuitry is provided to select the desired paths. During a synchronous and BE read operations, the first path of both the address and data register circuitry is selected. During BE write operations, the second path of the address register circuitry is selected. If the BE is operating in non-pipelined mode, the second path of the data register circuitry is selected.

Abstract: A substrate biasing circuit operates in either a test mode or a normal operating mode. The substrate biasing circuit includes a voltage generating circuit generating a substrate biasing voltage at an output terminal and a control terminal controlling the magnitude of the substrate voltage. When the voltage at the control terminal is more positive than a predetermined value, the voltage generating circuit gradually drives the substrate more negative. When the voltage at the control input of the voltage generating circuit is less than the predetermined value, the output terminal of the voltage generating circuit essentially floats. In normal operation, the output terminal of the voltage generating circuit is also coupled to the control terminal so that the substrate voltage is regulated at the predetermined negative voltage. Alternatively, the substrate may be coupled to ground and the voltage generating circuit disabled during normal operation.

Abstract: A semiconductor integrated circuit includes a biasing circuit connected to a plurality of memory cells via an access line. Each of the memory cells includes at least one switching device. The biasing circuit supplies a potential, having a value between a reference voltage and the threshold voltage of the switching device, to the access line for programming one of the memory cells to a logic low level.