Abstract: A semiconductor device has a substrate and first and second gate structures formed over a first surface of the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A sidewall spacer is formed over the first and second gate structures. A lateral LDD region is formed between the first and second gate structures. A trench is formed through the lateral LDD region and partially through the substrate self-aligned to the sidewall spacer. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited in the trench. A first source region is formed adjacent to the first gate structure opposite the lateral LDD region. A second source region is formed adjacent to the second gate structure opposite the lateral LDD region.

Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract: A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region.

Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract: Anti-fogging system for an endoscope including an endoscope having an outer housing, an imaging arrangement, and a distal window. A filter lens is located at the distal window, with the filter lens allowing a first portion of electromagnetic light to pass therethrough while absorbing a second portion of electromagnetic light in order to heat the filter lens.

Abstract: A method for determining the number of fingers on a sensing device, which has a plurality of scanlines, includes the steps of: identifying the scanlines that generate a detecting signal, which has a value greater than a threshold value; finding adjacent ones of the scanlines; forming at least one group from the adjacent ones of the scanlines thus found; and counting the number of the scanlines in the at least one group thus formed in order to determine the number of fingers on the sensing device.

Abstract: A touch sensing method includes: scanning a plurality of first and second sensor lines, aligned in two different directions, of a touch sensor board; generating first and second indications based on the scan result, the first/second indication carrying information of at least one group of the first/second sensor lines that are adjacent to one another on the touch sensor board and that have detected a user's touch on the touch sensor board and of a number of the first/second sensor lines in the group; and generating a status signal that corresponds to a predetermined finger gesture at least based on a comparison result determined by comparing the number of the first sensor lines indicated by the first indication with the number of the second sensor lines indicated by the second indication. An electronic device that implements the touch sensing method is also disclosed.

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Abstract: A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region.

Abstract: A semiconductor device has a substrate and first and second gate structures formed over a first surface of the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A sidewall spacer is formed over the first and second gate structures. A lateral LDD region is formed between the first and second gate structures. A trench is formed through the lateral LDD region and partially through the substrate self-aligned to the sidewall spacer. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited in the trench. A first source region is formed adjacent to the first gate structure opposite the lateral LDD region. A second source region is formed adjacent to the second gate structure opposite the lateral LDD region.

Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Abstract: A wireless operating room communication system provides wireless transmission of video signals from a wireless camera or a wireless transmitter unit to a portable wireless display unit. A wireless multiple device control unit is in wireless communication with the transmitter unit, the display unit, and a plurality of surgical devices disposed within the operating room. Each of the surgical devices has a video receiver to obtain a video signal to synchronize the devices and units. The video transmitter unit has a video transmitter and the other units or devices have a non-video transmitter. The arrangement enables transmission of device control signals on the same channel as the video signal. In response to changes in bandwidth, the video transmitter unit reduces the video signal to enable transmission thereof to the video display unit, while maintaining robustness of the control signals.

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Abstract: Operating system services are transparently triggered for thread execution resources (“sequencers”) that are sequestered from view of the operating system. A “surrogate” thread that is managed by, and visible to, the operating system is utilized to acquire OS services on behalf of a sequestered sequencer. Multi-shred contention for shred-specific resources may thus be alleviated. Other embodiments are also described and claimed.

Abstract: A multi-transformer LLC (resonant) power converter having at least two transformers including a first T1 and a second transformer T2 in series includes a switch network configured for receiving input power including a first and second switched node. Resonant circuitry is coupled between the first and second switched node including a series combination of an inductor, a capacitor, a primary winding of T1 and a primary winding of a T2. At least one switch is operable for providing a first mode that includes T2 in the resonant circuitry and a second mode that excludes T2 from the resonant circuitry. Secondary windings of T2 and T1 are connected electrically in parallel for driving an output capacitor (Co) through respective rectifiers which provide conversion from AC to DC.

Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.