Patents by Inventor John W. Smith

John W. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6821815
    Abstract: A method of encapsulating a microelectronic assembly comprises providing a microelectronic assembly having an element defining exterior surfaces and an array of terminals exposed at the exterior surfaces. The element defines an aperture through the exterior surfaces. A layer of a curable barrier material is screen printed onto a supporting element. The supporting element is assembled with the microelectronic assembly so that the layer of curable barrier material contacts the exterior surfaces and covers said one or more apertures. An encapsulant is applied to the microelectronic assembly.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: November 23, 2004
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Publication number: 20040219716
    Abstract: A method is disclosed for making a microelectronic package. A material is applied to a first major surface of a microelectronic element to reduce the heights of protrusions projecting from the first major surface. The microelectronic element is assembled to a microelectronic component. A method of forming protrusions and an assembly incorporating the microelectronic element having protrusions is also disclosed.
    Type: Application
    Filed: October 31, 2003
    Publication date: November 4, 2004
    Applicant: Tessera, Inc.
    Inventors: Michael Warner, Masud Beroz, David Light, Delin Li, Dennis Castillo, Hung-ming Wang, John W. Smith
  • Patent number: 6774306
    Abstract: A microelectronic assembly including elements such as a semiconductor chip and substrate has electrical connections between the elements incorporating fusible conductive metal masses. The fusible masses are surrounded and contained by a compliant material such as an elastomer or gel. The fusible material may melt during operation or processing of the device to relieve thermal cycling stress in the electrical connections.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 10, 2004
    Assignee: Tessera, Inc.
    Inventor: John W. Smith
  • Publication number: 20040075991
    Abstract: Electrical connections are made between a pair of elements disposed on opposite side of the hole extending through a dielectric layer by evaporating a conductive material such as a metal having high vapor pressure within the hole while maintaining the hole in a substantially sealed condition. The process may be performed simultaneously to form numerous connections within a microelectronic unit as, for example, within a multilayer circuit panel.
    Type: Application
    Filed: October 10, 2003
    Publication date: April 22, 2004
    Applicant: Tessera. Inc.
    Inventors: Belgacem Haba, John W. Smith
  • Publication number: 20040077129
    Abstract: An active microelectronic element such as a semiconductor chip or wafer is bonded to an interconnect element having substantially the same coefficient of thermal expansion as the active element using small, rigid bonds, desirably made by a solid-phase bonding technique, which accommodate numerous closely-spaced interconnections. The assembly is provided with terminals movable with respect to the active element and interconnect element. The interconnect element desirably provides low-impedance conductive paths interconnecting active electronic devices within the active element.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 22, 2004
    Applicant: Tessera, Inc.
    Inventors: John W. Smith, Belgacem Haba
  • Patent number: 6707149
    Abstract: A method of making a compliant microelectronic package includes providing a first substrate having a top surface with conductive pads and an opening extending therethrough to the first substrate so that a bottom surface of the second substrate confronts a top surface of the first substrate. A microelectronic element is attached to the first substrate so that a back face of the microelectronic element confronts the top surface of the first substrate. The contacts of the microelectronic element are electrically interconnected with the conductive pads of the second substrate. A dielectric sheet having conductive leads is juxtaposed with the first substrate. The second ends of the leads are electrically interconnected with the conductive pads of the second substrate, and the dielectric sheet and the second substrate are moved away from one another so as to vertically extend the leads.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: March 16, 2004
    Assignee: Tessera, Inc.
    Inventor: John W. Smith
  • Publication number: 20040048418
    Abstract: A method of making a compliant microelectronic package includes providing a first substrate having a top surface with conductive pads and an opening extending therethrough to the first substrate so that a bottom surface of the second substrate confronts a top surface of the first substrate. A microelectronic element is attached to the first substrate so that a back face of the microelectronic element confronts the top surface of the first substrate. The contacts of the microelectronic element are electrically interconnected with the conductive pads of the second substrate. A dielectric sheet having conductive leads is juxtaposed with the first substrate. The second ends of the leads are electrically interconnected with the conductive pads of the second substrate, and the dielectric sheet and the second substrate are moved away from one another so as to vertically extend the leads.
    Type: Application
    Filed: September 9, 2003
    Publication date: March 11, 2004
    Applicant: Tessera, Inc.
    Inventor: John W. Smith
  • Patent number: 6686015
    Abstract: A transferable resilient element assembly for fabricating a microelectronic package includes a first liner having a tacky material and a plurality of resilient elements, the plurality of resilient elements having a first surface being in contact with the the first liner. The plurality of resilient elements adhere to the tacky material so that upon removal of the plurality of resilient elements from the liner, the tacky material will adhere to the plurality of resilient elements and provide a tacky surface thereon.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: February 3, 2004
    Assignee: Tessera, Inc.
    Inventors: Kurt Raab, John W. Smith
  • Patent number: 6687842
    Abstract: A semiconductor chip is provided with a dielectric element having conductive features interconnecting electronic elements within the chip with one another. The conductive features replace internal conductors, and can provide enhanced signal propagation between elements of the chip. The conductive features on the dielectric element are connected to contacts on the chip by deformable conductive elements such as flexible leads so that the dielectric element remains movable with respect to the chip. The dielectric element may have a coefficient of expansion different from that of the chip itself.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: February 3, 2004
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith
  • Patent number: 6675469
    Abstract: Electrical connections are made between a pair of elements disposed on opposite side of the hole extending through a dielectric layer by evaporating a conductive material such as a metal having high vapor pressure within the hole while maintaining the hole in a substantially sealed condition. The process may be performed simultaneously to form numerous connections within a microelectronic unit as, for example, within a multilayer circuit panel.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: January 13, 2004
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, John W. Smith
  • Patent number: 6664621
    Abstract: An active microelectronic element such as a semiconductor chip or wafer is bonded to an interconnect element having substantially the same coefficient of thermal expansion as the active element using small, rigid bonds, desirably made by a solid-phase bonding technique, which accommodate numerous closely-spaced interconnections. The assembly is provided with terminals movable with respect to the active element and interconnect element. The interconnect element desirably provides low-impedance conductive paths interconnecting active electronic devices within the active element.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: December 16, 2003
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Belgacem Haba
  • Publication number: 20030207499
    Abstract: A component incorporating a dielectric element such as a polymeric film with leads and terminals thereon is assembled with a semiconductor chip and bond regions of the leads are connected to contacts of the chip. At least one lead incorporates a plural set of connecting regions connecting the bond region of that lead to a plurality of terminals. One or more of the connecting regions in each such plural set are severed so as to leave less than all of the terminals associated with each such plural set connected to the contacts of the chip.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 6, 2003
    Applicant: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Konstantine Karavakis, Craig S. Mitchell, John W. Smith
  • Patent number: 6635553
    Abstract: A microelectronic connection component includes a support such as a dielectric sheet having elongated leads extending along a surface. The leads have terminal ends permanently connected to the support and tip ends releasably connected to the support. The support is juxtaposed with a further element such as a semiconductor chip or wafer, and tip ends of the leads are bonded to contacts on the wafer using a bonding tool advanced through holes in the support. After bonding, the support and the further element are moved away from one another so as to deform the leads.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: October 21, 2003
    Assignee: Iessera, inc.
    Inventors: Thomas H. DiStefano, John W. Smith
  • Publication number: 20030192181
    Abstract: Microelectronic contacts, such as flexible, tab-like, cantilever contacts, are provided with asperities disposed in a regular pattern. Each asperity has a sharp feature at its tip remote from the surface of the contact. As mating microelectronic elements are engaged with the contacts, a wiping action causes the sharp features of the asperities to scrape the mating element, so as to provide effective electrical interconnection and, optionally, effective metallurgical bonding between the contact and the mating element upon activation of a bonding material.
    Type: Application
    Filed: April 17, 2003
    Publication date: October 16, 2003
    Inventors: Joseph Fjelstad, John W. Smith, Thomas H. DiStefano, James Zaccardi, A. Christian Walton
  • Patent number: 6627478
    Abstract: A microelectronic assembly is made by bonding the tip ends of leads on a first element to bonding contacts on a second element. The tip ends of the leads are releasably connected to the first element, so that the leads are held in place during the bonding process. After bonding, the first and second elements are heated or cooled to cause differential thermal expansion, which breaks at least some of the releasable attachments of the tip ends, leaving the leads free to flex.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: September 30, 2003
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Christopher M. Pickett
  • Publication number: 20030173107
    Abstract: A connection component including a flexible substrate having a top surface and a bottom surface, a layer of a compliant, dielectric material overlying the top surface of the substrate, the compliant material layer having a top surface remote from the substrate, an array of flexible, conductive leads having first ends attached to terminals accessible at the second surface of the substrate and second ends adjacent the top surface of the compliant layer, wherein each the lead comprises a core of a first conductive material surrounded by a layer of a second conductive material, the second conductive material having a greater yield strength than the first conductive material.
    Type: Application
    Filed: April 7, 2003
    Publication date: September 18, 2003
    Applicant: Tessera, Inc.
    Inventors: John W. Smith, Bruce McWilliams
  • Publication number: 20030150635
    Abstract: A microelectronic assembly including elements such as a semiconductor chip and substrate has electrical connections between the elements incorporating fusible conductive metal masses. The fusible masses are surrounded and contained by a compliant material such as an elastomer or gel. The fusible material may melt during operation or processing of the device to relieve thermal cycling stress in the electrical connections.
    Type: Application
    Filed: February 21, 2003
    Publication date: August 14, 2003
    Applicant: Tessera, Inc.
    Inventor: John W. Smith
  • Patent number: 6603209
    Abstract: The present invention provides a method for fabricating a compliant microelectronic device package and an associated apparatus for substantially obviating thermal, compliancy and interconnection problems. Flexible, dielectric layers are used having on a first surface a plurality conductive leads which are each electrically coupled at a first end to at least one conductive pad also coupled to the first surface of the dielectric layers. A second end of the conductive leads are further coupled between the dielectric layers across a bonding gap. A compliant layer is then coupled to the bottom surface of the dielectric layers. One of the dielectric layers is coupled to the surface of a die by one of the compliant layer such that the die bond pads are juxtaposed with respective leads in the bonding gap. This assembly is attached to a protective structure and is encapsulated. A solder mask may be placed over the exposed surface of the dielectric layers to cover the leads and prevent shoring.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: August 5, 2003
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Konstantine Karavakis, Craig Mitchell, John W. Smith
  • Patent number: D481226
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: October 28, 2003
    Assignee: Steelcase Development Corporation
    Inventors: Thomas Overthun, James N. Ludwig, David M. Gresham, Karl Heinz Mueller, Monika Conway, Stephen Don Wahl, John W. Smith
  • Patent number: D485096
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: January 13, 2004
    Assignee: Steelcase Development Corporation
    Inventors: Thomas Overthun, James N. Ludwig, David M. Gresham, Karl Heinz Mueller, Monika Conway, Stephen Don Wahl, John W. Smith