Patents by Inventor Johnny Widodo
Johnny Widodo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8716081Abstract: A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.Type: GrantFiled: March 15, 2007Date of Patent: May 6, 2014Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Shailendra Mishra, Johnny Widodo
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Patent number: 8274115Abstract: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.Type: GrantFiled: March 19, 2008Date of Patent: September 25, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lee Wee Teo, Chung Woh Lai, Johnny Widodo, Shyue Seng Tan, Shailendra Mishra, Zhao Lun, Yong Meng Lee, Jeffrey Chee
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Patent number: 8178417Abstract: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.Type: GrantFiled: April 22, 2008Date of Patent: May 15, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shailendra Mishra, James Yong Meng Lee, Zhao Lun, Wen Zhi Gao, Chung Woh Lai, Huang Liu, Johnny Widodo, Liang Choo Hsia
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Patent number: 8143651Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: GrantFiled: August 2, 2010Date of Patent: March 27, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Johnny Widodo, Liang Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun, Huang Liu, Chung Woh Lai, Shailendra Mishra, Yew Tuck Chow, Fang Chen, Shiang Yang Ong
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Patent number: 8053327Abstract: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.Type: GrantFiled: December 21, 2006Date of Patent: November 8, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shailendra Mishra, Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Johnny Widodo
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Patent number: 7999300Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.Type: GrantFiled: January 28, 2009Date of Patent: August 16, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Zhao Lun, James Yong Meng Lee, Lee Wee Teo, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo, Shailendra Mishra, Jeffrey Chee
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Publication number: 20110156110Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Inventors: Jun-jung Kim, Sang-jine Park, Min-ho Lee, Thomas W. Dyer, Sunfei Fang, O-sung Kwon, Johnny Widodo
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Patent number: 7932178Abstract: A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.Type: GrantFiled: December 28, 2006Date of Patent: April 26, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lee Wee Teo, Yong Meng Lee, Jeffrey Chee, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo, Zhao Lun, Shailendra Mishra
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Patent number: 7923365Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.Type: GrantFiled: October 17, 2007Date of Patent: April 12, 2011Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd., Infineon Technologies AGInventors: Jun-jung Kim, Sang-jine Park, Min-ho Lee, Thomas W. Dyer, Sunfei Fang, O-sung Kwon, Johnny Widodo
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Patent number: 7906426Abstract: An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.Type: GrantFiled: April 23, 2007Date of Patent: March 15, 2011Assignees: Globalfoundries Singapore Pte. Ltd., International Business Machines Corporation, Infineon Technologies AGInventors: Wuping Liu, Johnny Widodo, Teck Jung Tang, Jing Hui Li, Han Wah Ng, Larry A. Clevenger, Hermann Wendt
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Patent number: 7847402Abstract: A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.Type: GrantFiled: February 20, 2007Date of Patent: December 7, 2010Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd, Samsung Electronics Co., LtdInventors: Darryl D. Restaino, Griselda Bonilla, Christos D. Dimitrakopoulos, Stephen M. Gates, Jae H. Kim, Michael W. Lane, Xiao H. Liu, Son V. Nguyen, Thomas M. Shaw, Johnny Widodo
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Publication number: 20100301424Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: ApplicationFiled: August 2, 2010Publication date: December 2, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Johnny WIDODO, Liang Choo HSIA, James Yong Meng LEE, Wen Zhi GAO, Zhao LUN, Huang LIU, Chung Woh LAI, Shailendra MISHRA, Yew Tuck CHOW, Fang CHEN, Shiang Yang ONG
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Patent number: 7838390Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: GrantFiled: October 12, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
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Patent number: 7829422Abstract: A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing, such as curing medium used to form voids in an ultralow-k dielectric layer.Type: GrantFiled: December 22, 2006Date of Patent: November 9, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Johnny Widodo, Huang Liu, Sin Leng Lim
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Patent number: 7795680Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.Type: GrantFiled: December 7, 2007Date of Patent: September 14, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Huang Liu, Alex K. H. See, James Lee, Johnny Widodo, Chung Woh Lai, Wenzhi Gao, Zhao Lun, Shailendra Mishra, Liang-Choo Hsia
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Patent number: 7767577Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: GrantFiled: February 14, 2008Date of Patent: August 3, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Johnny Widodo, Liang Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun, Huang Liu, Chung Woh Lai, Shailendra Mishra, Yew Tuck Chow, Fang Chen, Shiang Yang Ong
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Publication number: 20100187587Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.Type: ApplicationFiled: January 28, 2009Publication date: July 29, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Zhao LUN, James Yong Meng LEE, Lee Wee TEO, Shyue Seng TAN, Chung Woh LAI, Johnny WIDODO, Shailendra MISHRA, Jeffrey CHEE
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Patent number: 7737029Abstract: Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 ? to about 50 ? and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.Type: GrantFiled: March 18, 2008Date of Patent: June 15, 2010Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.Inventors: Jae-hak Kim, Griselda Bonilla, Steven E. Molis, Darryl D. Restaino, Hosadurga Shobha, Johnny Widodo
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Publication number: 20100109155Abstract: A semiconductor device includes a dielectric layer in which an upper portion is densified. An interconnection is disposed in the dielectric layer. The densified portion reduces undercut during subsequent processing, improving reliability of the interconnection.Type: ApplicationFiled: November 5, 2008Publication date: May 6, 2010Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Huang LIU, Johnny WIDODO, Yihua WANG, Wuping LIU, Ti OUYANG, Wei LU
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Patent number: 7687381Abstract: Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.Type: GrantFiled: March 19, 2008Date of Patent: March 30, 2010Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.Inventors: Jae-hak Kim, Jing Hui Li, Wu Ping Liu, Johnny Widodo