Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.

Abstract: Mitigating effects of delamination of components in the data processing system is provided. A signal is received from one or more sensors in the data processing system. A determination is made as to whether the signal indicates that one threshold in a plurality of thresholds has been reached or exceeded. Responsive to the signal indicating that one threshold in the plurality of thresholds has been reached or exceeded, a determination is made as to whether the one threshold is a low temperature threshold or a high temperature threshold. Responsive to the one threshold being a low temperature threshold, one of a plurality of actions is initiated to increase a temperature of the data processing system thereby mitigating effects of delamination of the components in the data processing system.

Abstract: Monitoring temperature excursions an assembly experiences over a life of the assembly is provided. A determination is made as to whether the assembly has been in service beyond a predetermined end of life objective. Responsive to the assembly failing to be in service beyond the predetermined end of life objective, a new temperature value associated with the assembly is read. A modifier value for a figure of merit (FOM) value is computed and added to a cumulative figure of merit value. The cumulative figure of merit value is compared to a cumulative stress figure of merit budget. Responsive to the cumulative figure of merit value exceeding the cumulative stress figure of merit budget, an identified stress management solution is implemented.

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.

Abstract: A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer; and a plurality of via lands extending radially outward from the via stack, wherein each of the plurality of via lands is diametrically larger than the RFP cap. Preferably, the RFP cap comprises a diameter of at least 300 ?m. Preferably, each of the via lands comprises a substantially circular shape having a diameter of at least 400 ?m. Moreover, the circuit board further comprises a ball grid array pad connected to the via stack; and input/output ball grid array pads connected to the ball grid array pad. Additionally, the circuit board further comprises metal planes in the dielectric layer.

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.

Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.

Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.

Abstract: A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer; and a plurality of via lands extending radially outward from the via stack, wherein each of the plurality of via lands is diametrically larger than the RFP cap. Preferably, the RFP cap comprises a diameter of at least 300 ?m. Preferably, each of the via lands comprises a substantially circular shape having a diameter of at least 400 ?m. Moreover, the circuit board further comprises a ball grid array pad connected to the via stack; and input/output ball grid array pads connected to the ball grid array pad. Additionally, the circuit board further comprises metal planes in the dielectric layer.

Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).

Abstract: A low-k dielectric for use as an interlayer for an interconnect structure is provided. The dielectric of the present invention is an alkaline boron silicate glass which when formulated in certain compositional ranges can undergo spinodal decomposition when processed using certain thermal profiles. Spinodal decomposition is a chemical and physical separation of the silicate glass into a distinct interpenetrating microstructure which contains a substantially pure silicon dioxide network and a boron-rich network. The dimension (i.e., scale), and the amount of separation can be controlled through compositional and thermal control during the processing of the silicate glass.

Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

Abstract: A low-k dielectric for use as an interlayer for an interconnect structure is provided. The dielectric of the present invention is an alkaline boron silicate glass which when formulated in certain compositional ranges can undergo spinodal decomposition when processed using certain thermal profiles. Spinodal decomposition is a chemical and physical separation of the silicate glass into a distinct interpenetrating microstructure which contains a substantially pure silicon dioxide network and a boron-rich network. The dimension (i.e., scale), and the amount of separation can be controlled through compositional and thermal control during the processing of the silicate glass.