Patents by Inventor Jon Casey
Jon Casey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050176255Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.Type: ApplicationFiled: April 5, 2005Publication date: August 11, 2005Inventors: Jon Casey, James Balz, Michael Berger, Jerome Cohen, Charles Hendricks, Richard Indyk, Mark LaPlante, David Long, Lori Maiorino, Arthur Merryman, Glenn Pomerantz, Robert Rita, Krystyna Semkow, Patrick Spencer, Brian Sundlof, Richard Surprenant, Donald Wall, Thomas Wassick, Kathleen Wiley
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Publication number: 20050151213Abstract: A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).Type: ApplicationFiled: January 8, 2004Publication date: July 14, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jon Casey, William Ferrante, Edward Kiewra, Carl Radens, William Tonti
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Patent number: 6916670Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.Type: GrantFiled: February 4, 2003Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: Jon A. Casey, James G. Balz, Michael Berger, Jerome Cohen, Charles Hendricks, Richard Indyk, Mark LaPlante, David C. Long, Lori A. Maiorino, Arthur G. Merryman, Glenn A. Pomerantz, Robert A. Rita, Krystyna W. Semkow, Patrick E. Spencer, Brian R. Sundlof, Richard P. Surprenant, Donald R. Wall, Thomas A. Wassick, Kathleen M. Wiley
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Publication number: 20050148164Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.Type: ApplicationFiled: January 5, 2004Publication date: July 7, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JON CASEY, BRIAN SUNDLOF
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Publication number: 20050121768Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: ApplicationFiled: December 5, 2003Publication date: June 9, 2005Applicant: International Business Machines CorporationInventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker
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Publication number: 20050106834Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.Type: ApplicationFiled: November 3, 2003Publication date: May 19, 2005Inventors: Paul Andry, Jon Casey, Raymond Horton, Chiraq Patel, Edmund Sprogis, Brian Sundlof
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Publication number: 20050100743Abstract: A negative coefficient of thermal expansion particle includes a first bilayer having a first bilayer inner layer and a first bilayer outer layer, and a second bilayer having a second bilayer inner layer and a second bilayer outer layer. The first and second bilayers are joined together along perimeters of the first and second bilayer outer layers and first and second bilayer inner layers, respectively. The first bilayer inner layer and the second bilayer inner layer are made of a first material and the first bilayer outer layer and the second bilayer outer layer are made of a second material. The first material has a greater coefficient of thermal expansion than that of the second material.Type: ApplicationFiled: November 6, 2003Publication date: May 12, 2005Applicant: International Business Machines CorporationInventors: Gareth Hougham, Xiao Liu, S. Chey, James Doyle, Joseph Zinter, Michael Rooks, Brian Sundlof, Jon Casey
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Patent number: 6878616Abstract: A low-k dielectric for use as an interlayer for an interconnect structure is provided. The dielectric of the present invention is an alkaline boron silicate glass which when formulated in certain compositional ranges can undergo spinodal decomposition when processed using certain thermal profiles. Spinodal decomposition is a chemical and physical separation of the silicate glass into a distinct interpenetrating microstructure which contains a substantially pure silicon dioxide network and a boron-rich network. The dimension (i.e., scale), and the amount of separation can be controlled through compositional and thermal control during the processing of the silicate glass.Type: GrantFiled: November 21, 2003Date of Patent: April 12, 2005Assignee: International Business Machines CorporationInventors: Jon A. Casey, Daniel C. Edelstein
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Patent number: 6823585Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.Type: GrantFiled: March 28, 2003Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: Mark J. LaPlante, Jon A. Casey, Thomas A. Wassick, David C. Long, Krystyna W. Semkow, Patrick E. Spencer, Robert A. Rita, Richard F. Indyk, Kathleen M. Wiley, Brian R. Sundlof, James Balz, Lori A. Maiorino, Donald R. Wall, Glenn A. Pomerantz
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Publication number: 20040187303Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.Type: ApplicationFiled: March 28, 2003Publication date: September 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark J. LaPlante, Jon A. Casey, Thomas A. Wassick, David C. Long, Krystyna W. Semkow, Patrick E. Spencer, Robert A. Rita, Richard F. Indyk, Kathleen M. Wiley, Brian R. Sundlof, James Balz, Lori A. Maiorino, Donald R. Wall, Glenn A. Pomerantz
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Publication number: 20040148765Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.Type: ApplicationFiled: February 4, 2003Publication date: August 5, 2004Applicant: International Business Machines CorporationInventors: Jon A. Casey, James G. Balz, Michael Berger, Jerome Cohen, Charles Hendricks, Richard Indyk, Mark LaPlante, David C. Long, Lori A. Maiorino, Arthur G. Merryman, Glenn A. Pomerantz, Robert A. Rita, Krystyna W. Semkow, Patrick E. Spencer, Brian R. Sundlof, Richard P. Surprenant, Donald R. Wall, Thomas A. Wassick, Kathleen M. Wiley
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Patent number: 6562169Abstract: A method of processing greensheets, wherein the following steps are performed: a) providing a greensheet having a width, length, thickness, a first side and a second side; b) bonding to the first side of the greensheet at least one strip, wherein the strip lies in a first plane; c) bonding to the second side of the green sheet at least one strip, wherein the strip lies in a second plane; d) processing the greensheet; and e) removing the strips from the processed greensheet.Type: GrantFiled: January 17, 2001Date of Patent: May 13, 2003Assignee: International Business Machines CorporationInventors: Govindarajan Natarajan, Raschid J. Bezama, Jon A. Casey, Amy C. Flack, Robert W. Pasco, Arnold W. Terpening, Renee L. Weisman
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Publication number: 20030041966Abstract: A method of forming a laminated composite printed wiring structure of a plurality of at least three superimposed subcomposites having organic substrates is provided. Via openings in the subcomposite structures having conductive paste therein are positioned to align with openings in at least one adjacent subcomposite structure also filled with conductive paste that is to be joined thereto. Printed wiring is provided on at least one face of one subcomposite structure. A fixture with pins which extends through index openings in the composites are provided to mount masks for screening paste and stacking of the composites is provided. After screening of paste, and partially curing of the paste, in each composite, a group of composites is placed on the fixture and the pastes are fully cured to form a unitary structure.Type: ApplicationFiled: August 31, 2001Publication date: March 6, 2003Applicant: International Business Machines CorporationInventors: Jon A. Casey, Brian E. Curcio, John U. Knickerbocker, Voya R. Markovich, Mark D. Poliks
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Patent number: 6475555Abstract: A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.Type: GrantFiled: October 29, 1999Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Jon A. Casey, Dinesh Gupta, Lester Wynn Herron, John U. Knickerbocker, David C. Long, Jawahar P. Nayak, Brenda L. Peterson, Robert A. Rita
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Patent number: 6423174Abstract: The present invention relates generally to a new apparatus and method for forming cavities in semiconductor substrates without the necessity of using an insert. More particularly, the invention encompasses an apparatus and a method for fabricating cavities in semiconductor substrates wherein a coated membrane sheet is placed over the cavity prior to lamination and caused to conform to the contour of the cavity, thus preventing collapse of, or damage to, the cavity shelves during the lamination process. After the lamination process, the coated membrane is conveniently removed without causing damage to the cavity shelves or paste pull-outs.Type: GrantFiled: June 21, 1996Date of Patent: July 23, 2002Assignee: International Business Machines CorporationInventors: Jon A. Casey, Govindarajan Natarajan, Robert W. Pasco, Vincent P. Peterson
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Publication number: 20020092600Abstract: A method of processing greensheets, wherein the following steps are performed:Type: ApplicationFiled: January 17, 2001Publication date: July 18, 2002Applicant: International Business Machines CorporationInventors: Govindarajan Natarajan, Raschid J. Bezama, Jon A. Casey, Amy C. Flack, Robert W. Pasco, Arnold W. Terpening, Renee L. Weisman
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Patent number: 6413339Abstract: The present invention relates generally to a new metal/magnetic-ceramic laminate with through-holes and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area ceramic laminate magnet with a significant number of holes, integrated metal plate(s) and co-sintered electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display (MMD), and electron beam source, and methods of manufacture thereof.Type: GrantFiled: December 22, 1999Date of Patent: July 2, 2002Assignee: International Business Machines CorporationInventors: Govindarajan Natarajan, Jon A. Casey, Martin E. Klepeis, John U. Knickerbocker, Srinivasa S. N. Reddy, Robert A. Rita, Subhash L. Shinde
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Patent number: 6402866Abstract: A method and apparatus are provided for forming metal circuit patterns and other designs on greensheets and other substrates. The method and apparatus utilize a metal containing transfer sheet whereby selected portions of the metal containing transfer sheet are transferred to the greensheet forming the desired circuit pattern and then the transfer sheet removed. The metal containing transfer sheet may contain a release layer. Transfer methods include stamping, hot rolling, laser beam, heat, etc. and combinations thereof The transfer sheet may also have a stratified or graded vertical profile so that different conductivities or other circuit properties (transfer sheet adhesion, etc.) may be obtained in the formed pattern on the substrate.Type: GrantFiled: September 30, 1999Date of Patent: June 11, 2002Assignee: International Business Machines CorporationInventors: Jon A. Casey, John U. Knickerbocker, David C. Long, Brenda L. Peterson
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Publication number: 20020009539Abstract: A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.Type: ApplicationFiled: October 29, 1999Publication date: January 24, 2002Inventors: JON A. CASEY, DINESH GUPTA, LESTER WYNN HERRON, JOHN U. KNICKERBOCKER, DAVID C. LONG, JAWAHAR P. NAYAK, BRENDA L. PETERSON, ROBERT A. RITA
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Patent number: 6278049Abstract: Thermoelectric devices having enhanced thermal characteristics are fabricated using multilayer ceramic (MLC) technology methods. Aluminum nitride faceplates with embedded electrical connections provide the electrical series configuration for alternating dissimilar semiconducting materials. Embedded electrical connections are formed by vias and lines in the faceplate. A portion of the dissimilar materials are then melted within the tunnels to form a bond. Thermal conductivity of the faceplate is enhanced by adding electrically isolated vias to one surface, filled with high thermal conductivity metal paste. A low thermal conductivity material is also introduced between the two high thermal conductivity material faceplates.Type: GrantFiled: April 5, 2000Date of Patent: August 21, 2001Assignee: International Business Machines CorporationInventors: Gregory M. Johnson, Jon A. Casey, Scott R. Dwyer, David C. Long, Kevin M. Prettyman