Abstract: Powering random access memory (RAM) modules with non-volatile memory components may include providing, by a power supply, a first output voltage to one or more RAM modules, each RAM module of the one or more RAM modules comprising a volatile memory component and a non-volatile memory component; providing, by the power supply, a second output voltage to one or more system components distinct from the one or more RAM modules; detecting a power event; sending, by the power supply, in response to detecting the power event, a signal to the one or more RAM modules to initiate a save operation, wherein the save operation comprises storing, for each of the one or more RAM modules, data from the volatile memory component to the non-volatile memory component; and ceasing, by the power supply, the second output voltage while maintaining the first output voltage to facilitate the save operation.

Abstract: An apparatus for secure multiple server access to a non-volatile storage device is disclosed. A method and storage device product also perform the functions of the apparatus. An apparatus includes a storage device with three or more ports. Each port includes at least one lane and each port is configured to connect to a different server over the at least one lane of the port. The storage device includes a storage controller in the storage device for each port. Each storage controller controls storage to non-volatile storage of the storage device. The storage device includes a logical namespace assigned to each port. Each logical namespace is assigned to a portion of the non-volatile storage of the storage device. The logical namespace of a first port of the three or more ports is inaccessible to a second port of the three or more ports.

Abstract: An apparatus includes a root port for coupling to a root complex, and a plurality of endpoint ports for coupling to endpoint devices, wherein each endpoint port is associated with a function number. A downstream buffer queues transaction layer packets (TLPs) received from the root port, wherein each TLP in the downstream buffer is directed to an endpoint port associated with the identified function number. An upstream buffer queues TLPs received from each endpoint port, and directs the queued TLPs to the root port. A method includes associating a function number with each endpoint port of a switch, wherein each endpoint port is adapted for coupling to an endpoint device. The method further includes receiving a first TLP from a root complex, identifying a function number within the first TLP, and directing the first TLP to an endpoint device through the endpoint port associated with the identified function number.

Abstract: An apparatus for cache coherency between a device and a processor includes a buffer module that buffers data in a non-cache coherent space of an electronic device communicatively coupled to a processor. The apparatus includes an update module that updates at least one identifier with respect to the buffered data. The at least one identifier is stored in a cache coherent space of the electronic device. The apparatus includes a coherence notification module that notifies the processor of a cache incoherence. The cache incoherence indicates that the cache coherent space of the electronic device that includes the updated at least one identifier differs from a cache coherent space of the processor that includes a copy of the at least one identifier prior to the update.

Abstract: Powering random access memory (RAM) modules with non-volatile memory components may include providing, by a power supply, a first output voltage to one or more RAM modules, each RAM module of the one or more RAM modules comprising a volatile memory component and a non-volatile memory component; providing, by the power supply, a second output voltage to one or more system components distinct from the one or more RAM modules; detecting a power event; sending, by the power supply, in response to detecting the power event, a signal to the one or more RAM modules to initiate a save operation, wherein the save operation comprises storing, for each of the one or more RAM modules, data from the volatile memory component to the non-volatile memory component; and ceasing, by the power supply, the second output voltage while maintaining the first output voltage to facilitate the save operation.

Abstract: An apparatus for secure multiple server access to a non-volatile storage device is disclosed. A method and storage device product also perform the functions of the apparatus. An apparatus includes a storage device with three or more ports. Each port includes at least one lane and each port is configured to connect to a different server over the at least one lane of the port. The storage device includes a storage controller in the storage device for each port. Each storage controller controls storage to non-volatile storage of the storage device. The storage device includes a logical namespace assigned to each port. Each logical namespace is assigned to a portion of the non-volatile storage of the storage device. The logical namespace of a first port of the three or more ports is inaccessible to a second port of the three or more ports.

Abstract: A method, computer program product and apparatus are provided. For example, the method includes receiving, by a first data storage device within a storage area network, input output operations over a first network pathway within the storage area network. The method further includes receiving, by the first data storage device, a migration instruction that identifies a second data storage device within the storage area network and a source volume stored on the first data storage device. Still further, the method includes migrating, by the first data storage device, the source volume directly to the second data storage device over a second network pathway within the storage area network.

Abstract: An apparatus includes a root port for coupling to a root complex, and a plurality of endpoint ports for coupling to endpoint devices, wherein each endpoint port is associated with a function number. A downstream buffer queues transaction layer packets (TLPs) received from the root port, wherein each TLP in the downstream buffer is directed to an endpoint port associated with the identified function number. An upstream buffer queues TLPs received from each endpoint port, and directs the queued TLPs to the root port. A method includes associating a function number with each endpoint port of a switch, wherein each endpoint port is adapted for coupling to an endpoint device. The method further includes receiving a first TLP from a root complex, identifying a function number within the first TLP, and directing the first TLP to an endpoint device through the endpoint port associated with the identified function number.

Abstract: An apparatus includes a root port for coupling to a root complex, and a plurality of endpoint ports for coupling to endpoint devices, wherein each endpoint port is associated with a function number. A downstream buffer queues transaction layer packets (TLPs) received from the root port, wherein each TLP in the downstream buffer is directed to an endpoint port associated with the identified function number. An upstream buffer queues TLPs received from each endpoint port, and directs the queued TLPs to the root port. A method includes associating a function number with each endpoint port of a switch, wherein each endpoint port is adapted for coupling to an endpoint device. The method further includes receiving a first TLP from a root complex, identifying a function number within the first TLP, and directing the first TLP to an endpoint device through the endpoint port associated with the identified function number.

Abstract: An apparatus for cache coherency between a device and a processor includes a buffer module that buffers data in a non-cache coherent space of an electronic device communicatively coupled to a processor. The apparatus includes an update module that updates at least one identifier with respect to the buffered data. The at least one identifier is stored in a cache coherent space of the electronic device. The apparatus includes a coherence notification module that notifies the processor of a cache incoherence. The cache incoherence indicates that the cache coherent space of the electronic device that includes the updated at least one identifier differs from a cache coherent space of the processor that includes a copy of the at least one identifier prior to the update.

Abstract: An apparatus includes a memory device for storing program instructions and a processor for processing the program instructions to: receive a host data storage command that includes a host namespace, a host memory pointer and a logical block address range; translate the host data storage command into a plurality of disk data storage commands, wherein each disk data storage command is uniquely identified with a disk namespace on one of a plurality of non-volatile memory devices; and send, for each of the plurality of disk data storage commands, the disk data storage command to the non-volatile memory device that includes the uniquely identified disk namespace.

Abstract: A method, computer program product and apparatus are provided. For example, the method includes receiving, by a first data storage device within a storage area network, input output operations over a first network pathway within the storage area network. The method further includes receiving, by the first data storage device, a migration instruction that identifies a second data storage device within the storage area network and a source volume stored on the first data storage device. Still further, the method includes migrating, by the first data storage device, the source volume directly to the second data storage device over a second network pathway within the storage area network.

Abstract: A method, apparatus and computer program product are provided. For example, a computer program product may include a computer readable storage medium that is not a transitory signal having program instructions embodied therewith, the program instructions executable by a processor to: receive a bid request from a storage manager, wherein the bid request identifies a volume parameter of a volume to be created; determine a bid based on the current capacity of a data storage device to host the identified volume; and send the bid to the storage manager.

Abstract: An apparatus includes a root port for coupling to a root complex, and a plurality of endpoint ports for coupling to endpoint devices, wherein each endpoint port is associated with a function number. A downstream buffer queues transaction layer packets (TLPs) received from the root port, wherein each TLP in the downstream buffer is directed to an endpoint port associated with the identified function number. An upstream buffer queues TLPs received from each endpoint port, and directs the queued TLPs to the root port. A method includes associating a function number with each endpoint port of a switch, wherein each endpoint port is adapted for coupling to an endpoint device. The method further includes receiving a first TLP from a root complex, identifying a function number within the first TLP, and directing the first TLP to an endpoint device through the endpoint port associated with the identified function number.

Abstract: A memory device and memory system using the memory device. The memory system includes a memory controller having a memory bus with a plurality of lanes, and a plurality of memory devices. Each memory device has a plurality of data pins and a plurality of detection circuits, wherein each detection circuit is coupled to one of the data pins to detect whether the data pin is coupled to one of the lanes of the memory bus. Each lane of the memory bus provides a point-to-point connection between the memory controller and exactly one of the device data lanes, wherein a subset of the data lanes of each memory device are coupled to one of the lanes of the memory bus. The memory capacity of a memory system may be increased by using more of the memory devices limited only by the width of the memory bus.

Abstract: A memory device and memory system using the memory device. The memory system includes a memory controller having a memory bus with a plurality of lanes, and a plurality of memory devices. Each memory device has a plurality of data pins and a plurality of detection circuits, wherein each detection circuit is coupled to one of the data pins to detect whether the data pin is coupled to one of the lanes of the memory bus. Each lane of the memory bus provides a point-to-point connection between the memory controller and exactly one of the device data lanes, wherein a subset of the data lanes of each memory device are coupled to one of the lanes of the memory bus. The memory capacity of a memory system may be increased by using more of the memory devices limited only by the width of the memory bus.

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level.

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract: A memory device is provided comprising: a volatile memory device, a non-volatile memory device, a memory control circuit volatile memory controller coupled to the volatile memory device and non-volatile memory device, and a backup power source. The backup power source may be arranged to temporarily power the volatile memory devices and the memory control circuit upon a loss of power from the external power source. Additionally, a switch may serve to selectively couple: (a) a host memory bus to either the volatile memory device or non-volatile memory device; and (b) the volatile memory device to the non-volatile memory device. Upon reestablishment of power by an external power source from a power loss event, the memory control circuit is configured to restore data from the non-volatile memory device to the volatile memory device prior to a host system, to which the memory device is coupled, completes boot-up.