Patents by Inventor Jonathan W. Greene
Jonathan W. Greene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230181779Abstract: A sterilization, disinfection, sanitization, or decontamination system having a chamber defining a region, and a generator for creating a free radical effluent with reactive oxygen, nitrogen, and other species and/or a vaporizer. A closed loop circulating system without a free-radical destroyer is provided for supplying the mixture of free radicals from the generator mixed with the hydrogen peroxide solution in the form of the effluent to the chamber. The system is used in sterilizing, disinfecting, sanitizing, or decontaminating items in the chamber or room and, with a wound chamber, in treating wounds on a body. The wound chamber may be designed to maintain separation from wounds being treated. Various embodiments can control moisture to reduce or avoid unwanted condensation. Some embodiments can be incorporated into an appliance having a closed space, such as a washing machine. Some embodiments may include a residual coating device that deposits a bactericidal coating on sterilized items.Type: ApplicationFiled: January 5, 2022Publication date: June 15, 2023Inventors: Czeslaw Golkowski, Rick Shea, Jonathan W. Greene, Mark Golkowski, Anya Golkowski, Tom Steffie
-
Patent number: 11671099Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y?q, where q is a pre-determined value (e.g., such as 0 or 1).Type: GrantFiled: November 18, 2021Date of Patent: June 6, 2023Assignee: Microchip Technology Inc.Inventors: Jonathan W. Greene, Marcel Derevlean
-
Publication number: 20230116391Abstract: A method and apparatus for embedding a microprocessor in a programmable logic device (PLD), where the microprocessor has a logic unit that can operate in two modes. A first mode is a general purpose mode running at least one general purpose process related to the PLD, and a second mode is a fixed function mode emulating a fixed function for use by logic configured into a fabric of the PLD (fabric). A memory unit is coupled to the logic unit and to the fabric, and the fabric is operable for transferring signals with the logic unit in relation to the fixed function.Type: ApplicationFiled: June 28, 2022Publication date: April 13, 2023Applicant: Microchip Technology Inc.Inventors: Aaron Severance, Jonathan W. Greene, Joel Vandergriendt
-
Patent number: 11544349Abstract: A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.Type: GrantFiled: April 15, 2021Date of Patent: January 3, 2023Assignee: Microsemi SoC Corp.Inventors: John L. McCollum, Jonathan W. Greene, Gregory William Bakker
-
Publication number: 20220382945Abstract: A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.Type: ApplicationFiled: May 10, 2022Publication date: December 1, 2022Applicant: Microchip Technology Inc.Inventors: Jonathan W. Greene, Gabriel Barajas, Fei Li, Hassan Hassan, James Sumit Tandon
-
Publication number: 20220378961Abstract: A sterilization, disinfection, sanitization, or decontamination system having a chamber defining a region, and a generator for creating a free radical effluent with reactive oxygen, nitrogen, and other species and/or a vaporizer. A closed loop circulating system without a free-radical destroyer is provided for supplying the mixture of free radicals from the generator mixed with the hydrogen peroxide solution in the form of the effluent to the chamber. The system is used in sterilizing, disinfecting, sanitizing, or decontaminating items in the chamber or room and, with a wound chamber, in treating wounds on a body. The wound chamber may be designed to maintain separation from wounds being treated. Various embodiments can control moisture to reduce or avoid unwanted condensation. Some embodiments can be incorporated into an appliance having a closed space, such as a washing machine. Some embodiments may include a residual coating device that deposits a bactericidal coating on sterilized items.Type: ApplicationFiled: April 27, 2022Publication date: December 1, 2022Inventors: Czeslaw Golkowski, Rick Shea, Jonathan W. Greene, Mark Golkowski, Danwei Ye, Robert Allen, Ben Parker, Sergey Makarov, Jason R. Ertel
-
Publication number: 20220376693Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y?q, where q is a pre-determined value (e.g., such as 0 or 1).Type: ApplicationFiled: November 18, 2021Publication date: November 24, 2022Applicant: Microchip Technology Inc.Inventors: Jonathan W. Greene, Marcel Derevlean
-
Patent number: 11344643Abstract: A sterilization, disinfection, sanitization, or decontamination system having a chamber defining a region, and a generator for creating a free radical effluent with reactive oxygen, nitrogen, and other species and/or a vaporizer. A closed loop circulating system without a free-radical destroyer is provided for supplying the mixture of free radicals from the generator mixed with the hydrogen peroxide solution in the form of the effluent to the chamber. The system is used in sterilizing, disinfecting, sanitizing, or decontaminating items in the chamber or room and, with a wound chamber, in treating wounds on a body. The wound chamber may be designed to maintain separation from wounds being treated. Various embodiments can control moisture to reduce or avoid unwanted condensation. Some embodiments can be incorporated into an appliance having a closed space, such as a washing machine. Some embodiments may include a residual coating device that deposits a bactericidal coating on sterilized items.Type: GrantFiled: October 24, 2018Date of Patent: May 31, 2022Assignee: Sterifre Medical, Inc.Inventors: Czeslaw Golkowski, Rick Shea, Jonathan W. Greene, Mark Golkowski, Danwei Ye, Robert Allen, Ben Parker, Sergey Makarov, Jason R. Ertel
-
Patent number: 11253620Abstract: A sterilization, disinfection, sanitization, or decontamination system having a chamber defining a region, and a generator for creating a free radical effluent with reactive oxygen, nitrogen, and other species and/or a vaporizer. A closed loop circulating system without a free-radical destroyer is provided for supplying the mixture of free radicals from the generator mixed with the hydrogen peroxide solution in the form of the effluent to the chamber. The system is used in sterilizing, disinfecting, sanitizing, or decontaminating items in the chamber or room and, with a wound chamber, in treating wounds on a body. The wound chamber may be designed to maintain separation from wounds being treated. Various embodiments can control moisture to reduce or avoid unwanted condensation. Some embodiments can be incorporated into an appliance having a closed space, such as a washing machine. Some embodiments may include a residual coating device that deposits a bactericidal coating on sterilized items.Type: GrantFiled: June 15, 2017Date of Patent: February 22, 2022Assignee: Sterifre Medical, Inc.Inventors: Czeslaw Golkowski, Rick Shea, Jonathan W. Greene, Mark Golkowski, Anya Golkowski, Tom Steffie
-
Publication number: 20210232658Abstract: A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Applicant: Microsemi SoC Corp.Inventors: John L. McCollum, Jonathan W. Greene, Gregory William Bakker
-
Patent number: 11023559Abstract: A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.Type: GrantFiled: March 14, 2019Date of Patent: June 1, 2021Assignee: Microsemi SoC Corp.Inventors: John L. McCollum, Jonathan W. Greene, Gregory William Bakker
-
Patent number: 10971216Abstract: A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.Type: GrantFiled: November 1, 2018Date of Patent: April 6, 2021Assignee: Microsemi SoC Corp.Inventors: Jonathan W. Greene, John McCollum
-
Patent number: 10936286Abstract: A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.Type: GrantFiled: January 8, 2019Date of Patent: March 2, 2021Assignee: Microsemi SoC Corp.Inventors: Jonathan W. Greene, Joel Landry
-
Publication number: 20200242190Abstract: A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.Type: ApplicationFiled: March 14, 2019Publication date: July 30, 2020Inventors: John L. McCollum, Jonathan W. Greene, Gregory William Bakker
-
Patent number: 10714180Abstract: A configuration memory cell includes a latch portion including a cross-coupled latch having complementary output nodes, and a programmable read-only memory (PROM) portion coupled to one of the complementary output nodes of the latch portion, the PROM portion including a programmable and erasable ReRAM device.Type: GrantFiled: January 16, 2019Date of Patent: July 14, 2020Assignee: Microsemi SoC Corp.Inventors: John L McCollum, Jonathan W. Greene
-
Publication number: 20200150925Abstract: A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.Type: ApplicationFiled: January 8, 2019Publication date: May 14, 2020Applicant: Microsemi SoC Corp.Inventors: Jonathan W. Greene, Joel Landry
-
Patent number: 10523208Abstract: A 4-input lookup table module including eight first-rank 2-input multiplexers, four second-rank multiplexers, two third-rank multiplexers, and one fourth-rank multiplexer, the first-rank through fourth-rank multiplexers forming a tree structure. A select input of the fourth-rank multiplexer is coupled to a first input node. Select inputs of the third-rank multiplexers are coupled to a second input node. Select inputs of a first and a second adjacent ones of the second rank 2-input multiplexers are electrically isolated from select inputs of a third and a fourth adjacent ones of the second rank 2-input multiplexers. Select inputs of a first through a fourth adjacent ones of the first rank 2-input multiplexers are electrically isolated from select inputs of a fifth through an eighth adjacent ones of the first rank 2-input multiplexers.Type: GrantFiled: October 31, 2018Date of Patent: December 31, 2019Assignee: Microsemi SoC Corp.Inventors: Volker Hecht, Jonathan W. Greene
-
Publication number: 20190237139Abstract: A configuration memory cell includes a latch portion including a cross-coupled latch having complementary output nodes, and a programmable read-only memory (PROM) portion coupled to one of the complementary output nodes of the latch portion, the PROM portion including a programmable and erasable ReRAM device.Type: ApplicationFiled: January 16, 2019Publication date: August 1, 2019Applicant: Microsemi SoC Corp.Inventors: John L. McCollum, Jonathan W. Greene
-
Patent number: 10361702Abstract: An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.Type: GrantFiled: October 31, 2018Date of Patent: July 23, 2019Assignee: Microsemi SoC Corp.Inventors: Jonathan W. Greene, Fei Li
-
Publication number: 20190190522Abstract: An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.Type: ApplicationFiled: October 31, 2018Publication date: June 20, 2019Applicant: Microsemi SoC Corp.Inventors: Jonathan W. Greene, Fei Li