Abstract: A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.

Abstract: A 4-input lookup table module including eight first-rank 2-input multiplexers, four second-rank multiplexers, two third-rank multiplexers, and one fourth-rank multiplexer, the first-rank through fourth-rank multiplexers forming a tree structure. A select input of the fourth-rank multiplexer is coupled to a first input node. Select inputs of the third-rank multiplexers are coupled to a second input node. Select inputs of a first and a second adjacent ones of the second rank 2-input multiplexers are electrically isolated from select inputs of a third and a fourth adjacent ones of the second rank 2-input multiplexers. Select inputs of a first through a fourth adjacent ones of the first rank 2-input multiplexers are electrically isolated from select inputs of a fifth through an eighth adjacent ones of the first rank 2-input multiplexers.

Abstract: A multi-state static RAM cell includes N NOR gates. Each NOR gate has N?1 inputs and one output. The output of each NOR gate is coupled to a different bit line. Each NOR gate has its inputs connected to the outputs of each of the other NOR gates.

Abstract: A multi-state static RAM cell includes N NOR gates. Each NOR gate has N-1 inputs and one output. The output of each NOR gate is coupled to a different bit line. Each NOR gate has its inputs connected to the outputs of each of the other NOR gates.

Abstract: An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write-probe data input path to the asynchronous data input line of each flip flop, a write-probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.

Abstract: An integrated circuit includes a clock input, a first output, and a second output. A programmable pulse generator has a programmable pulse counter coupled to the clock input at least one control input for receiving count information. A fixed delay element is coupled to the programmable pulse counter. A programmable delay element is coupled to the programmable pulse counter and has at least one control input for receiving delay information. A first multiplexer is coupled to the fixed delay element, the programmable delay element and to the first output. A second multiplexer is coupled to the programmable delay element, the output of the fixed delay element and the second output.

Abstract: An integrated circuit includes a clock input, a first output, and a second output. A programmable pulse generator has a programmable pulse counter coupled to the clock input at least one control input for receiving count information. A fixed delay element is coupled to the programmable pulse counter. A programmable delay element is coupled to the programmable pulse counter and has at least one control input for receiving delay information. A first multiplexer is coupled to the fixed delay element, the programmable delay element and to the first output. A second multiplexer is coupled to the programmable delay element, the output of the fixed delay element and the second output.

Abstract: An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write-probe data input path to the asynchronous data input line of each flip flop, a write-probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.

Abstract: An I/O scheme for an integrated circuit includes a group layout cell. The group layout cell includes a plurality of signal I/O pads. A driver circuit is coupled to each signal I/O pad. The group layout cell also includes two I/O driver-circuit power-supply pads. ESD protection circuitry is coupled to the plurality of driver circuits. The signal I/O pads and the I/O driver-circuit power-supply pads are arranged in rows. The rows may be regular or staggered.

Abstract: A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

Abstract: A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

Abstract: A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

Abstract: A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

Abstract: A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

Abstract: An integrated circuit die has a plurality of I/O cells disposed about its periphery, each I/O cell having an I/O bonding pad. A first group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the first group of I/O cells having an I/O pad disposed thereon and spaced at a first distance from the periphery of the die. A second group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the second group of I/O cells having an I/O pad disposed thereon and spaced at a distance from the periphery of the die more than the first distance, the distance increasing as a function of the proximity of each I/O cell to a corner of the die.

Abstract: A reduced-leakage interconnect circuit includes a buffer having an input and an output, at least one multiplexer transistor coupled between a multiplexer input node and the input of the buffer, and a fixed-state multiplexer transistor coupled between a fixed-state multiplexer input node and the input of the buffer, the fixed-state multiplexer input node having a potential of either less than zero volts or more than VCC present on it.