Patents by Inventor Jong-Mil Youn
Jong-Mil Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11581435Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: GrantFiled: June 8, 2020Date of Patent: February 14, 2023Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Patent number: 11575014Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising an element isolation region and an active region defined by the element isolation region, a fin-type pattern on the active region, the fin-type pattern extending in a first horizontal direction, a gate electrode on the fin-type pattern, the gate electrode extending in a second horizontal direction that crosses the first horizontal direction, a capping pattern on the gate electrode, a source/drain region on at least one side of the gate electrode, a source/drain contact on the source/drain region and electrically connected to the source/drain region, and a filling insulating layer on the source/drain contact, the filling insulating layer having a top surface at a same level as a top surface of the capping pattern, and including a material containing a carbon (C) atom.Type: GrantFiled: April 12, 2021Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Deok Han Bae, Sung Min Kim, Ju Hun Park, Myung Yoon Um, Jong Mil Youn
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Publication number: 20220077292Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising an element isolation region and an active region defined by the element isolation region, a fin-type pattern on the active region, the fin-type pattern extending in a first horizontal direction, a gate electrode on the fin-type pattern, the gate electrode extending in a second horizontal direction that crosses the first horizontal direction, a capping pattern on the gate electrode, a source/drain region on at least one side of the gate electrode, a source/drain contact on the source/drain region and electrically connected to the source/drain region, and a filling insulating layer on the source/drain contact, the filling insulating layer having a top surface at a same level as a top surface of the capping pattern, and including a material containing a carbon (C) atom.Type: ApplicationFiled: April 12, 2021Publication date: March 10, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Deok Han BAE, Sung Min KIM, Ju Hun PARK, Myung Yoon UM, Jong Mil YOUN
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Publication number: 20210272950Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.Type: ApplicationFiled: May 14, 2021Publication date: September 2, 2021Inventors: DAE-LIM KANG, HYUN-JO KIM, JONG-MIL YOUN, SOO-HUN HONG
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Patent number: 11011511Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.Type: GrantFiled: October 22, 2018Date of Patent: May 18, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Lim Kang, Hyun-Jo Kim, Jong-Mil Youn, Soo-Hun Hong
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Publication number: 20200303547Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Patent number: 10714614Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: GrantFiled: August 22, 2018Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Publication number: 20190385915Abstract: A semiconductor device includes a substrate including at least a first region, first active patterns and a first dummy pattern which vertically protrude from the first region, a device isolation layer filling a first trench, a second trench and a third trench of the substrate, and a gate electrode intersecting the first active patterns. The first trench defines the first active patterns on the first region, the second trench defines a first sidewall of the first region, and the third trench defines a second sidewall of the first region, which is opposite to the first sidewall. A sidewall of the first dummy pattern is aligned with the second sidewall of the first region, and a level of a top of the second sidewall of the first region is higher than a level of a top of the first sidewall of the first region.Type: ApplicationFiled: January 16, 2019Publication date: December 19, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Youngmin PARK, Kyoung Hwan YEO, Jong Mil YOUN, Hwasung RHEE
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Publication number: 20190081035Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.Type: ApplicationFiled: October 22, 2018Publication date: March 14, 2019Inventors: DAE-LIM KANG, HYUN-JO KIM, JONG-MIL YOUN, SOO-HUN HONG
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Publication number: 20180366582Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: ApplicationFiled: August 22, 2018Publication date: December 20, 2018Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Patent number: 10153270Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.Type: GrantFiled: January 19, 2015Date of Patent: December 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Lim Kang, Hyun-Jo Kim, Jong-Mil Youn, Soo-Hun Hong
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Patent number: 10084088Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: GrantFiled: June 9, 2017Date of Patent: September 25, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Patent number: 10032886Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.Type: GrantFiled: June 1, 2016Date of Patent: July 24, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Yup Chung, Hyun-Jo Kim, Seong-Yul Park, Se-Wan Park, Jong-Mil Youn, Jeong-Hyo Lee, Hwa-Sung Rhee, Hee-Don Jeong, Ji-Yong Ha
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Patent number: 9929155Abstract: A semiconductor device and a method of manufacturing the same are disclosed, which may improve the operating performance of a multi-gate transistor in a highly scaled integrated circuit device. The semiconductor device includes a first active fin unit protruding on a first region of a semiconductor substrate and extending along a first direction. The first active fin unit includes at least one first active fin having left and right profiles, which are symmetric to each other about a first center line perpendicular to a top surface of the semiconductor substrate on a cut surface perpendicular to the first direction. A second active fin unit protrudes on a second region of the semiconductor substrate and includes two second active fins, each having a left and right profiles, which are asymmetric to each other about a second center line perpendicular to the top surface of the semiconductor substrate on a cut surface.Type: GrantFiled: December 30, 2015Date of Patent: March 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-youn Kim, Jong-mil Youn
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Patent number: 9922979Abstract: An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.Type: GrantFiled: February 3, 2016Date of Patent: March 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-yup Chung, Jong-shik Yoon, Hwa-sung Rhee, Hee-don Jeong, Je-Min Yoo, Kyu-man Cha, Jong-mil Youn, Hyun-jo Kim
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Publication number: 20170278966Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: ApplicationFiled: June 9, 2017Publication date: September 28, 2017Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Patent number: 9698264Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: GrantFiled: January 8, 2016Date of Patent: July 4, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Publication number: 20160380075Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.Type: ApplicationFiled: June 1, 2016Publication date: December 29, 2016Inventors: Jae-Yup CHUNG, Hyun-Jo KIM, Seong-Yul PARK, Se-Wan PARK, Jong-Mil YOUN, Jeong-Hyo LEE, Hwa-Sung RHEE, Hee-Don JEONG, Ji-Yong HA
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Patent number: 9515182Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: GrantFiled: December 16, 2015Date of Patent: December 6, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Patent number: 9502417Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: GrantFiled: February 18, 2016Date of Patent: November 22, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha