Abstract: A circuit package for a microwave signal comprises a substrate defining a MMIC surface of the substrate and an opposing non-MMIC surface of the substrate. The substrate is devoid of signal carrying vias. A waveguide is disposed on the MMIC surface of the substrate. A MMIC is disposed on the MMIC surface of the substrate, and the MMIC is in electrical communication with the waveguide. An I/O port is in electrical communication with the waveguide wherein a transmission path for the signal is provided from the I/O port, through the waveguide and to the MMIC. In an alternative exemplary embodiment of the invention, the I/O port of the circuit package is electrically connectable to a PC board. The MMIC surface of the substrate faces the PC board when the I/O port is electrically connected to the PC board.

Abstract: A circuit package for a microwave signal comprises a substrate defining a MMIC surface of the substrate and an opposing non-MMIC surface of the substrate. The substrate is devoid of signal carrying vias. A waveguide is disposed on the MMIC surface of the substrate. A MMIC is disposed on the MMIC surface of the substrate, and the MMIC is in electrical communication with the waveguide. An I/O port is in electrical communication with the waveguide wherein a transmission path for the signal is provided from the I/O port, through the waveguide and to the MMIC. In an alternative exemplary embodiment of the invention, the I/O port of the circuit package is electrically connectable to a PC board. The MMIC surface of the substrate faces the PC board when the I/O port is electrically connected to the PC board.

Abstract: A low cost microwave circuit package having high performance characteristics is disclosed. The package operates in the frequency range up to 90 GHz while requiring less space on the printed circuit board. Space savings is provided by small components and the leadless design of the package. Taking the place of leads is a ball grid array and RF ports. An unlimited number of layout designs are possible within an ?s! matrix close to ##EQU1## within the operating frequency band of the package, for any pair of signal transmission ports.

Abstract: A method and apparati for improved filling of via holes wherein compressive force is used to columnate conductive material due to a pseudoplastic thixotropic rheology of the material. Columnating of the material provides for easier and more accurate filling of via holes. Both automated roller apparati and manual methods are provided. The method further includes methods and apparati of removing excess conductive material from substrates after filling the via holes.

Abstract: A multiple resonant frequency decoupling capacitor is presented. The decoupling capacitor comprises a plurality of capacitive elements, each having a different resonant frequency to define a frequency bandwidth for noise supression. One of the capacitive elements having a resonant frequency indicative of the clock frequency of an integrated circuit being decoupled by the capacitor. Further, at least one other capacitive element having a resonant frequecny indicative of a harmonic frequency of the clock frequency.

Abstract: A decoupling scheme is presented which is particularly well suited for use with integrated circuit packages having internal cavities for receiving an integrated circuit chip such as Pin Grid Array (PGA) packages, ceramic dual-in-line packages, ceramic flat packs and ceramic leadless chip carriers. In accordance with the present invention, a decoupling capacitor (which preferably comprises a very thin high capacitance layer made by a thick film or thin film process sandwiched between an inner and outer electrode layer) is positioned within the internal cavity of an integrated circuit package such as a PGA package and electrically connected to the IC chip within the cavity. In a particularly preferred embodiment, the decoupling capacitor has a novel configuration for improved heat transfer. This novel configuration includes a pair of parallel plate electrodes wherein the upper electrode has extended flaps which wrap around the top surface of the decoupling capacitor.

Abstract: A decoupling scheme is presented which is well suited for use with any type of integrated circuit package. In accordance with the present invention, a flat decoupling capacitor is attached directly to the top of an IC die and is electrically connected to the IC by means of raised conductive bumps provided either on the surface of the decoupling capacitor or on the IC die surface. These conductive bumps interconnect the internal electrodes of the capacitor to the power and ground circuits of the IC. The resulting decoupling scheme provides a decoupling loop with an inductance which is significantly lower than previously disclosed decoupling loops.

Abstract: A molded integrated circuit package includes an integrated circuit chip, a heat sink device attached directly to the chip or lead frame and a molded package encapsulating the chip. The heat sink preferably comprises a thermally conductive material having a stem which communicates between the IC chip and the exterior of the molded package for direct conduction of heat from the IC chip to the exterior of the package.

Abstract: A multilayer printed wiring board is presented for surface mounting or through hole technology, which includes one or more layers of a high capacitance flexible dielectric sheet material. The dielectric sheet is comprised of a monolayer of multilayer or single layer high dielectric constant (e.g. ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (e.g. ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces. The board of the present invention alleviates the need for decoupling capacitors, thus resulting in significant, space savings on the board surface.

Abstract: A bus bar is presented which sandwiches a high capacitance flexible dielectric sheet material between the conductive layers. The high capacitance dielectric sheet is comprised of a monolayer of multilayer or single layer high dielectric (e.g. ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (e.g. ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces. The whole structure is then sandwiched between two conductive layers. The result is a bus bar with a very low characteristic impedance.

Abstract: A rugged, highly reliable, leadless decoupling capacitor is provided which may be positioned between a circuit board and an integrated circuit package including, for example, a leaded surface mounted IC package or Pin Grid Array package. This decoupling capacitor is comprised of a rugged ceramic or like substrate having printed or otherwise applied thereon a very thin high capacitance layer made by thick or thin film processes which is sandwiched between two thin electrode layers. Conductive castellations extend from the electrode layers along the surface of the ceramic substrate for connection to the circuit board. Preferably, an electrically insulative protective layer encapsulates the capacitor. The dielectric layer preferably comprises a high dielectric glass/ceramic dielectric paste or dielectric sol-gel layer. The overall thickness of the decoupling capacitor may be less than 0.020 inch.

Abstract: A decoupling capacitor is attached directly to an IC lead frame and thereafter encapsulated within a molded package along with an IC chip resulting in a decoupling scheme which is internal to the molded IC package. The capacitor preferably comprises a thin layer of ceramic dielectric sandwiched between top and bottom conductors. The top conductor may be attached to the die bar of the lead frame using an electrically non-conductive or conductive adhesive. Leads extending from the capacitors are attached to appropriate fingers of the lead frame by welding, soldering or the like to effect strong mechanical and electrical contact.

Abstract: A decoupling scheme which is particularly well suited for use with molded integrated circuit packages incorporating lead frames is presented. In accordance with the present invention, a thin decoupling capacitor is used which is comprised of a ceramic or like substrate having printed or otherwise applied thereon conductive layers, dielectric layers (e.g., glass/ceramic dielectric paste or dielectric sol-gel) and protective layers. Mounted on this thin capacitor is an integrated circuit chip. This thin capacitor/IC chip assembly is attached directly to the IC lead frame and thereafter encapsulated within the molded package resulting in a decoupling scheme which is internal to the molded IC package. Printed conductors on the thin capacitor's ceramic substrate are attached to appropriate fingers of the lead frame by welding, soldering or the like to effect strong mechanical and electrical contact.

Abstract: A high capacitance flexible dielectric sheet material is comprised of a monolayer of multilayer or single layer high dielectric (for example ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (for example ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces. The end result is a relatively flexible high capacitance dielectric film or sheet material which is drillable, platable, printable, etchable, laminable and reliable.

Abstract: The temperature characteristics of each of the layers in a multilayer ceramic capacitor are adjusted (through chemical doping of the basic dielectric material) to thereby stagger the temperature characteristics (e.g. curie points). As a result, the composite temperature characteristic of the multilayer structure will be much more stable than that of any individual layer. The temperature characteristics of the individual layers will combine in an additive manner thereby achieving the objective of high capacitance and uniform temperature stability for materials which have high dielectric constant but poor temperature stability. Thus, by properly formulating the composition of the layers of a multilayer ceramic chip capacitor, relative temperature stability of capacitance and high volumetric capacitance efficiency will be achieved.

Abstract: A multilayer capacitor is presented which provides high capacitance and low inductance. The capacitor comprises a plurality of conductive layers, each separated from the other and sandwiching therebetween a high capacitance flexible dielectric sheet material. The dielectric sheet material is comprised of a monolayer of multilayer or single layer high dielectric (e.g. ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (e.g. ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces.

Abstract: A decoupling capacitor is presented which is particularly useful in conjunction with either pin grid array type IC packages or with plastic leaded chip carrier IC packages. In accordance with the present invention, the multiplicity of elongated conductors of prior art decoupling capacitors are replaced with flat, wide conductive strips termed herein as skirts. These skirts extend outwardly from the top and bottom conductors of the decoupling capacitor and include small leads extendng therefrom which are solely for the purpose of either insertion into the circuit board or for connection with a surface pad on the circuit board. Thus, rather than the multiplicity of elongated leads found in the prior art, the present invention utilizes flat strips or skirts having very small leads extending therefrom. This skirt construction provides far lower inductance relative to the elongated leads of the prior art.

Abstract: High frequency noise is decoupled from power supplied to a surface mounted integrated circuit (IC) leadless chip carrier package by installation of a surface mounted decoupling capacitor over the IC chip carrier package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit over a surface mounted integrated circuit (IC) leadless chip carrier package and correspond to the power and ground pin configuration of that package.

Abstract: A multilayer printed wiring board is presented for surface mounting or through hole technology, which includes one or more layers of a high capacitance flexible dielectric sheet material. The dielectric sheet is comprised of a monolayer of multilayer or single layer high dielectric constant (e.g. ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (e.g. ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces. The board of the present invention alleviates the need for decoupling capacitors, thus resulting in significant, space savings on the board surface.

Abstract: A novel and improved device for interconnecting an integrated circuit package to a circuit board is presented. In accordance with the present invention an integrated circuit package having an central area devoid of surface contacts is positioned over a resilient or compressible connector system. The compressible connector includes an opening about its center which corresponds to the central area on the integrated circuit package. A component is mounted on the circuit board within the opening of the compressible connector between the integrated circuit package and the circuit board.