Abstract: A hermetically sealed and automatically insertable decoupling capacitor for use in conjunction with integrated circuit DIP inserter devices having a multi-layer ceramic capacitor chip provided with conductive electrodes on the top and bottom surfaces thereof sandwiched between suitable conductive strips and insulating layers and retained within an opening formed in an insulating strip by solder or conductive adhesive. The multi-layer ceramic capacitor further includes conductive end terminations having insulative caps thereon to prevent shorting.

Abstract: High frequency noise is decoupled from power supplied to Pin Grid Array (PGA), surface mounted leaded chip carrier and surface mounted leadless chip carrier packages by insertion of a decoupling capacitor between the PGA or leaded chip carrier package and printed circuit board; or by mounting the decoupling capacitor over a leadless chip carrier package. The decoupling capacitor comprises a multi layer capacitive element sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a PGA or leaded chip carrier package, or over a leadless chip carrier package; and correspond to the power and ground pin or lead configuration of that PGA, surface mounted leaded chip carrier and surface mounted leadless chip carrier package.

Abstract: Several embodiments of a decoupling capacitor are described which incorporate at least one multilayer capacitive element and which utilize metallized dielectric (i.e., ceramic) substrates rather than a pair of conductors. Also, several types of multilayer ceramic capacitor elements are disclosed which provide a low induction parallel-plate type capacitive structure. The decoupling capacitor assemblies of the present invention are specifically sized and configured so as to be either received in the space directly below the integrated circuit chip and between the downwardly extending pins of a PGA package or "leaded" chip carrier package or to be mounted directly over a "leadless" chip carrier package.

Abstract: Several constructions of multilayer ceramic capacitor elements are presented which provide a low induction parallel-plate type capacitive structure.

Abstract: High frequency noise is decoupled from power supplied to a Pin Grid Array (PGA) package by insertion of a decoupling capacitor between the PGA package and printed circuit board. The decoupling capacitor comprises a multi layer capacitive element sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a PGA package and correspond to the power and ground pin configuration of that PGA package.

Abstract: High frequency noise is decoupled from power supplied to a surface mounted integrated circuit (IC) chip carrier package by installation of a surface mounted decoupling capacitor between the IC chip carrier package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of surface mountable leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a surface mounted integrated circuit (IC) chip carrier package and correspond to the power and ground pin configuration of that package.

Abstract: A decoupling capacitor and method of manufacture thereof are presented wherein the decoupling capacitor is formed from a lead frame which contains the four leads of the capacitor (two of which are electrically inactive) on a single plane. The use of a lead frame automatically provides the dimensional tolerances necessary for encapsulation molding of the decoupling capacitor. The decoupling capacitor is a hermetically sealed capacitive unit consisting of a single layer ceramic capacitor, active leads bonded to the capacitor and dummy pins for auto-insertion into printed circuit boards.

Abstract: High frequency noise is decoupled from power supplied to a Pin Grid Array (PGA) package by insertion of a decoupling capacitor between the PGA package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a PGA package and correspond to the power and ground pin configuration of that PGA package.

Abstract: A decoupling capacitor is presented including a pair of conductors, each having a lead connected thereto formed from a continuous strip of electrically conductive material (lead frame), the strip having opposing planar surfaces. A pair of dummy leads, each being associated with a conductor, but isolated therefrom, is also formed from the strip. Thereafter, a strip of first insulating material is positioned across from one opposing surface of the conductive strip and a strip of second insulating material having a plurality of openings or windows therein is positioned on the other opposing surface of the conductive strip. The two insulating layers sandwiching the conductive strip are then heat tacked and hot press laminated to form a continuous strip of laminated material. The windows are positioned on the conductive strip to define access opening for the two conductors.

Abstract: A decoupling capacitor and method of manufacture thereof are presented wherein the decoupling capacitor is provided with inactive or dummy-pins to facilitate automatic insertion of the decoupling capacitor to printed circuit boards.