Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate (i) a first series of sequential frames, (ii) a plurality of local motion vectors for each of said frames, (iii) one or more global motion vectors for each of said frames, (iv) a second series of stabilized sequential frames, (v) a plurality of rough motion vectors and (vi) a digital bitstream in response to (i) a video input signal. The second circuit may be configured to store (i) the first series of sequential frames, (ii) the plurality of local motion vectors, (iii) the one or more global motion vectors, (iv) the second series of stabilized sequential frames and (v) the plurality of rough motion vectors.

Abstract: A camera comprising a first circuit and a second circuit. The first circuit may be configured to perform image signal processing using encoding related information. The second circuit may be configured to encode image data using image signal processing related information. The first circuit may be further configured to pass the image signal processing related information to the second circuit. The second circuit may be further configured to pass the encoding related information to the first circuit. The second circuit may be further configured to modify one or more motion estimation processes based upon the information from the first circuit.

Abstract: In some embodiments, content-category-level encoding statistical indicators (statistics) are assigned to weighted linear combinations of corresponding macroblock-level statistics. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A given macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Macroblock-level encoding parameters are generated by combining content-category-level parameters.

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel.

Abstract: In some embodiments, encoding modes for a video image block are enabled according to similarity measures of the block with respect to multiple content categories. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. In a priority mode, the encoding modes specified by a priority content category (e.g. a red category) are selectively enabled for the block, regardless of the block's similarity to other (non-priority) content categories, provided the block is sufficiently similar to the priority category. In a dominant mode, the encoding modes enabled by a maximum-similarity content category are enabled for the block. In an all-inclusive mode, any mode enabled by any sufficiently-similar content category is enabled for the block. Enabled encoding modes may be further evaluated for selection for the block. Encoding modes may include inter/intra modes, macroblock partition sizes, and intra-prediction directions.

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to perform image signal processing using encoding related information. The second circuit may be configured to encode image data using image signal processing related information, wherein said first circuit is further configured to pass said image signal processing related information to said second circuit and said second circuit is further configured to pass said encoding related information to said first circuit.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to perform image signal processing using encoding related information. The second circuit may be configured to encode image data using image signal processing related information, wherein said first circuit is further configured to pass said image signal processing related information to said second circuit and said second circuit is further configured to pass said encoding related information to said first circuit.

Abstract: A camera including a first circuit and a second circuit. The first circuit may be configured to perform image signal processing and control one or more functions of the camera using image signal processing related information and encoding related information. The second circuit may be configured to encode image data using the image signal processing related information and camera settings information. The first circuit may be further configured to pass the image signal processing related information and the camera settings information to the second circuit. The second circuit may be further configured to pass the encoding related information to the first circuit.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) receive an image data stream comprising a plurality of frames each having a plurality of regions, (ii) select a particular region to be marked as being homogeneous or not homogeneous, and (iii) determine whether a group of neighboring regions to the selected region are qualified or not qualified. The second circuit may be configured to mark the selected region as being homogeneous when one or more of the adjacent regions are (i) qualified and (ii) previously marked as being homogeneous.

Abstract: A method for image decoding is disclosed. The method generally includes the steps of (A) receiving from a medium (1) an encoded signal and (2) transform data comprising at least one of (i) encoding statistics embedded in the encoded signal, (ii) encoding information and (iii) pre-processing information, wherein (a) the encoding statistics are created by an encoder in encoding an intermediate input signal to create the encoded signal, (b) the encoding information is producible by the encoder in the encoding and (c) the pre-processing information is producible by a pre-processor in converting an image input signal into the intermediate input signal, (B) generating an intermediate output signal by decoding the encoded signal and (C) generating an image output signal by processing the intermediate output signal in response to the transform data.

Abstract: A method and apparatus are disclosed for performing motion estimation and compensation to fractional pixel accuracy using polyphase prediction filters as part of a video compression/decompression technique. A motion estimator applies a set of polyphase filters to some data in the reference picture and generates motion vectors, an estimated macroblock of video data, and a residual error macroblock of video data. The data referenced in the reference picture usually have more data than a macroblock since multi-tap filtering needs to access more data. A motion compensator generates a compensated macroblock of video data in response to the reference video data, the residual error macroblock of video data, and a polyphase prediction filter decided by the motion vector. The reference video data are usually reconstructed at the compensator side.

Abstract: An apparatus comprising an edge detector circuit, an edge strength detector and an edge strength threshold circuit. The edge detector circuit may be configured to determine a plurality of default directions of a macroblock in response to a plurality of input signals comprising information about a plurality of samples in the macroblock. The edge strength detector circuit may be configured to generate a maximum strength signal and a next maximum strength signal in response to the default directions. The edge strength threshold circuit may be configured to generate an edge direction signal and an edge strength signal in response to the maximum strength signal and the next maximum strength signal. The edge direction signal may comprise (i) any one of the default directions when in a first state and (ii) any one of a plurality of intermediate directions when in a second state.

Abstract: A method and apparatus are disclosed for adaptively selecting a deblocking filter used in video de-blocking. Determinations are made as to whether each of a set of spatially adjacent video blocks is inter-coded or intra-coded and whether each of said adjacent video blocks is field-coded or frame-coded. A deblocking filter is selected (an interlace deblocking filter or a frame deblocking filter) based on the determinations. The selected deblocking filter is used to filter across a boundary between adjacent video blocks.

Abstract: A method is provided for displaying progressive video content on an interlaced display device. The method comprises vertically phase shifting video lines of the progressive video content to correctly position the video lines with respect to a video field of the interlaced display device. The method further comprises scaling the video lines of progressive video content to match a vertical size of a video field of the interlaced display device.

Abstract: A method and system are disclosed for vertically phase shifting fields of at least one interlaced frame of video into at least two vertically aligned frames of video. The at least two vertically aligned frames of video are compressed, transmitted or stored, decompressed, and phase shifted a second time to generate at least one interlaced frame of video.

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel.

Abstract: System and method of data unit management in a decoding system employing a decoding pipeline. Each incoming data unit is assigned a memory element and is stored in the assigned memory element. Each decoding module gets the data to be operated on, as well as the control data, for a given data unit from the assigned memory element. Each decoding module, after performing its decoding operations on the data unit, deposits the newly processed data back into the same memory element. In one embodiment, the assigned memory locations comprise a header portion for holding the control data corresponding to the data unit and a data portion for holding the substantive data of the data unit. The header information is written to the header portion of the assigned memory element once and accessed by the various decoding modules throughout the decoding pipeline as needed. The data portion of memory is used/shared by multiple decoding modules.