Abstract: Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor interface. In one embodiment, other decoding accelerators, in addition to the variable-length decoder, are adapted to provide status data indicative of their status to a co-processor status register. In another embodiment, a decoding accelerator is controlled by providing commands to the accelerator via posted write operations and polling the accelerator to determine whether the command has been performed. In still another embodiment, a first hardware accelerator communicates with a core decoder processor via a co-processor interface and other decoding accelerators, in addition to the first hardware accelerator, are adapted to provide status data indicative of their status to a co-processor status register.

Abstract: Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor interface. In one embodiment, other decoding accelerators, in addition to the variable-length decoder, are adapted to provide status data indicative of their status to a co-processor status register. In another embodiment, a decoding accelerator is controlled by providing commands to the accelerator via posted write operations and polling the accelerator to determine whether the command has been performed. In still another embodiment, a first hardware accelerator communicates with a core decoder processor via a co-processor interface and other decoding accelerators, in addition to the first hardware accelerator, are adapted to provide status data indicative of their status to a co-processor status register.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract: A method and apparatus are disclosed for polyphase filtering a first number of vertical lines of video data to generate a second number of vertical lines of video data and then polyphase filtering the second number of vertical lines of video data to re-create the first number of vertical lines of video data. The first number of vertical lines is larger than the second number of vertical lines. The polyphase filtering of the first number of vertical lines includes low-pass filtering and sample rate converting (down-converting) the first number of vertical lines to the second number of vertical lines. The polyphase filtering of the second number of vertical lines includes sample rate converting (up-sampling) the second number of vertical lines to the first number of vertical lines. Between the down-sampling and the up-sampling, video compression and de-compression may also be performed using, for example, standard compression and de-compression techniques.

Abstract: A method and system are disclosed for vertically phase shifting fields of at least one interlaced frame of video into at least two vertically aligned frames of video. The at least two vertically aligned frames of video are compressed, transmitted or stored, decompressed, and phase shifted a second time to generate at least one interlaced frame of video.

Abstract: A method and apparatus are disclosed for adaptively selecting a deblocking filter used in video de-blocking. Determinations are made as to whether each of a set of spatially adjacent video blocks is inter-coded or intra-coded and whether each of said adjacent video blocks is field-coded or frame-coded. A deblocking filter is selected (an interlace deblocking filter or a frame deblocking filter) based on the determinations. The selected deblocking filter is used to filter across a boundary between adjacent video blocks.

Abstract: A method is provided for displaying progressive video content on an interlaced display device. The method comprises vertically phase shifting video lines of the progressive video content to correctly position the video lines with respect to a video field of the interlaced display device. The method further comprises scaling the video lines of progressive video content to match a vertical size of a video field of the interlaced display device.

Abstract: A method and apparatus are disclosed for performing motion estimation and compensation to fractional pixel accuracy using polyphase prediction filters as part of a video compression/decompression technique. A motion estimator applies a set of polyphase filters to some data in the reference picture and generates motion vectors, an estimated macroblock of video data, and a residual error macroblock of video data. The data referenced in the reference picture usually have more data than a macroblock since multi-tap filtering needs to access more data. A motion compensator generates a compensated macroblock of video data in response to the reference video data, the residual error macroblock of video data, and a polyphase prediction filter decided by the motion vector. The reference video data are usually reconstructed at the compensator side.

Abstract: Copy protection is provided for the now-unprotected computer monitor port of a computer 100 in two ways: (i) delaying synchronizing signals by a time variable amount and (ii) generating pulses during non-active video. Delay of the synchronizing signal is performed by selecting a fixed offset 203 and selecting either the fixed offset of the pseudorandom delay to be sent to a variable delay generator 260, which delays the horizontal synchronizing signal 201 by the selected amount. This new delayed horizontal synchronizing signal 202 is encoded by the CRT Controller 244 and is then sent to the computer monitor 164, which uses the delayed synchronizing signal 202 as encoded to produce its display in conjunction with a data signal. Thus, if these signals 202, 268 are intercepted by a VGA to TV converter 122, the converter 122 (or any downstream device) is unable to lock onto the correct frequency in order to reproduce the image properly.