Abstract: Aspects of this disclosure relate to driving a capacitive micromachined ultrasonic transducer (CMUT) with a pulse train of unipolar pulses. The CMUT may be electrically excited with a pulse train of unipolar pulses such that the CMUT operates in a continuous wave mode. In some embodiments, the CMUT may have a contoured electrode.

Abstract: Aspects of this disclosure relate to driving a capacitive micromachined ultrasonic transducer (CMUT) with a pulse train of unipolar pulses. The CMUT may be electrically excited with a pulse train of unipolar pulses such that the CMUT operates in a continuous wave mode. In some embodiments, the CMUT may have a contoured electrode.

Abstract: Aspects of this disclosure relate to a capacitive micromachined ultrasonic transducer (CMUT) with a contoured electrode. In certain embodiments, the CMUT has a contoured electrode. The electrode may be non-planar to correspond to a deflected shape of the outer plate. A change in distance between the electrode and the plate after deflection may be greater than a minimum threshold across the width of the CMUT.

Abstract: Aspects of this disclosure relate to driving a capacitive micromachined ultrasonic transducer (CMUT) with a pulse train of unipolar pulses. The CMUT may be electrically excited with a pulse train of unipolar pulses such that the CMUT operates in a continuous wave mode. In some embodiments, the CMUT may have a contoured electrode.

Abstract: Aspects of this disclosure relate to a capacitive micromachined ultrasonic transducer (CMUT) with a contoured electrode. In certain embodiments, the CMUT has a contoured electrode. The electrode may be non-planar to correspond to a deflected shape of the outer plate. A change in distance between the electrode and the plate after deflection may be greater than a minimum threshold across the width of the CMUT.

Abstract: Aspects of this disclosure relate to driving a capacitive micromachined ultrasonic transducer (CMUT) with a pulse train of unipolar pulses. The CMUT may be electrically excited with a pulse train of unipolar pulses such that the CMUT operates in a continuous wave mode. In some embodiments, the CMUT may have a contoured electrode.

Abstract: A method and apparatus for grouping video tracks in a video editing timeline comprises displaying a plurality of video tracks in a video editing timeline; receiving a selection of video tracks to be grouped from the plurality of video tracks that are displayed; displaying the video tracks selected for grouping as a single video track in the video editing timeline; and applying an indicator identifying the video tracks as grouped in the video editing timeline.

Abstract: Methods and apparatus provide for a self-enclosed timeline trimmer to create a circular timeline placed over a video that graphically represents the entire duration of a video. The self-enclosed timeline trimmer generates a self-enclosed timeline to represent a duration of the video incremented according to a first unit of time. The self-enclosed timeline is layered over at least a portion of the video. The self-enclosed timeline trimmer represents a start of the video on the self-enclosed timeline and an end of the video on the self-enclosed timeline. The self-enclosed timeline trimmer displays the duration of the video in its entirety by connecting the start and the end of the video on the self-enclosed timeline. Further, the self-enclosed timeline trimmer is well suited for video editing on mobile computer devices, wireless computer devices, and for portable computer devices.

Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.

Abstract: A method and apparatus for grouping video tracks in a video editing timeline comprises displaying a plurality of video tracks in a video editing timeline; receiving a selection of video tracks to be grouped from the plurality of video tracks that are displayed; displaying the video tracks selected for grouping as a single video track in the video editing timeline; and applying an indicator identifying the video tracks as grouped in the video editing timeline.

Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.

Abstract: A portable RFID (Radio Frequency Identification) tag includes one or more sensors. Each sensor measures a condition of an environment within which the RFID tag is disposed. Circuitry obtains data from measurements provided by each sensor. A transceiver modulates a radio frequency (RF) signal carrying the obtained data. An antenna, electrically coupled to the transceiver, transmits the RF signal. The circuitry, transceiver, and antenna are potted in their entirety in a thermosetting plastic epoxy for purposes of enduring extreme environmental conditions. The one or more sensors can include a temperature probe. A portion of this temperature probe can serve as the antenna.

Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.

Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.

Abstract: Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.

Abstract: Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.

Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.