Abstract: A CMOS impedance matching circuit includes an amplifier and a feedback circuit. The amplifier allows control of the impedance by controlling the V/I characteristic. The amplifier is sized to provide the desired impedance. The feedback circuit clamps the maximum excursions of the input signal, thereby maximizing signal speed. It also provides a higher impedance to noise beyond the dead band. In one embodiment of the present invention, the amplifier includes an amplifier circuit in parallel with an amplifier buffer. The amplifier buffer provides no gain and simply performs the inverting function when no gain is required for impedance matching. In one embodiment, the amplifier circuit includes a plurality of switchable amplifiers coupled in parallel with each other. Each of the switchable amplifiers has a different gain, and the one with the right amount of gain for the needed impedance matching is chosen using control inputs.

Abstract: A delay-locked loop includes a phase detection circuit, a charge pump circuit and a phase shift circuit. The phase detection circuit is coupled to receive a first signal and a second signal. The phase detection circuit generates a phase-error output signal indicative of whether the first signal is ahead of or behind the second signal in phase responsive to receiving the first and second signals. The charge pump circuit is coupled to receive a phase-error signal derived from the phase-error output signal. The charge pump circuit generates a plurality of control output signals. Each of the control output signals are based upon the phase-error signal and by at least one signal derived from one other of the control output signals. The phase shift circuit is coupled to receive a plurality of control input signals and a plurality of periodic input signals. The control input signals are derived from the control output signals. Each of the periodic input signals have a different phase.

Abstract: A projector headlamp utilizing only a single HID bulb for projecting light in a forward direction generally along a horizontal axis selectably between low beam and high beam conditions while shifting the hot spot as required between these conditions.

Abstract: An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes a reference circuit and a comparison circuit. The reference circuit is coupled to a first node having the first voltage and a second node having the second voltage to generate a reference signal from the first and second voltages. The reference circuit includes at least one instance of a first electrical characteristic cell. The comparison circuit is coupled to receive a feedback clock signal and to generate a comparison signal therefrom. The comparison circuit includes at least one instance of the first electrical characteristic cell. The duty cycle error measurement circuit is coupled to receive the reference signal and the comparison signal.

Abstract: A method and apparatus for providing equalization for a communication channel is provided. The invention uses edge transition samples, such as those obtained for phase detection in a phase locked loop (PLL) circuit, to determine the amount of equalization to be applied to signals received from a communication channel. By monitoring run lengths of consecutive identical bits received from the communication channel, the invention provides equalization for various frequency components present in the receive signal. One embodiment of the invention subtracts a weighted RC-filtered version of the receive signal from the unfiltered receive signal to provide an equalized receive signal. In this embodiment, a control circuit that monitors the received run lengths and edge transition information adjusts the resistance of the RC filter to adapt the equalization to the data being received and the potentially time varying conditions for the communication channel.

Abstract: An apparatus for suppressing the effect of noise from a first circuit on the performance of a second circuit wherein the first and second circuits are on a common substrate. Each of the first and second circuits include first and second supply rails. The apparatus includes a noise isolation circuit and a noise transference circuit. The noise isolation circuit is for coupling the first supply rails of the first and second circuits to prevent noise on the first supply rail of the first circuit from transferring to the first supply rail of the second circuit. The noise transference circuit is for coupling the second supply rails of the first and second circuits so that noise on the second supply rail of the first circuit is transferred to the second supply rail of the second circuit.

Abstract: A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In addition, the LC oscillator is operable over a range of frequencies sufficient to support both normal full power operation, and reduced power operation of the microprocessor. The LC oscillator minimizes clock jitter problems and so permits extension of the microprocessor operating frequency to even higher levels than heretofore were possible. An output signal from a phase-frequency detector is a frequency control signal on a frequency control input line of a level converter and filter circuit of the LC oscillator. The output signal from level converter and filter circuit is a filtered frequency control signal on a control voltage input line to a continuously modifiable gigahertz frequency voltage controlled oscillator (VCO) circuit.

Abstract: An on-chip resistance to an input current of an input signal includes a parallel transistor resistor and a control circuit for biasing the transistors of the parallel transistor resistor. The parallel transistor resistor includes first and second transistors of first and second types. Each transistor includes first and second current handling terminals and a control terminal. The control terminals are coupled to receive control signals from the control circuit. The first current handling terminals are coupled to provide an input node for receiving an input signal, and the second current handling terminals are coupled to provide an output signal. The control circuit is coupled to provide the first and second control signals for biasing the respective first and second transistors so that a first derivative of a resistance of the parallel transistor resistor in relation to an input-to-output voltage is zero at a selectable operation point.

Abstract: In a sample-and-hold circuit, an input is tracked at an output during a tracking period and the input is held during an holding period, the tracking period and holding period defined by a clock signal input to the sample-and-hold circuit, wherein the output is a differential output having a positive output node and a negative output node with the output signal represented by a voltage difference from the negative output node to the positive output node. During the tracking period, an equalizing transistor between the output nodes is turned on to bring the output to a common mode level for the output. During the holding period, the equalizing transistor is turned off and a regenerative circuit drives the output nodes apart, thus amplifying the input signal.