Abstract: A power amplifier system includes a transistor stack and an upper portion. The upper portion includes an LC tank. The LC tank is configured to generate selected harmonics to mitigate voltage stress and facilitate amplifier efficiency. The transistor stack includes serial connected input transistors and upper transistors. The input transistors are configured to receive an input signal and the upper transistors are configured to provide an amplifier output signal. The LC tank is configured to provide the selected harmonics to at least gates of the upper transistors.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: A power amplifier system includes a transistor stack and an upper portion. The upper portion includes an LC tank. The LC tank is configured to generate selected harmonics to mitigate voltage stress and facilitate amplifier efficiency. The transistor stack includes serial connected input transistors and upper transistors. The input transistors are configured to receive an input signal and the upper transistors are configured to provide an amplifier output signal. The LC tank is configured to provide the selected harmonics to at least gates of the upper transistors.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: A digital-to-analog conversion arrangement for converting a digital input signal comprises first and second digital-to-analog converters (DACs) having different signal resolutions and a digital-to-analog converter selector for selecting the first DAC or the second DAC if the digital input signal has a power in a first or a second power range, respectively. The digital-to-analog conversion arrangement further comprises an analog signal merger for merging a first analog signal and a second analog signal, the first analog signal being based on a first analog output signal of the first digital-to-analog converter and the second analog signal being based on a second analog output signal of the second analog-to-digital converter. A corresponding method for digital-to-analog conversion of a digital input signal and a computer readable digital storage medium are also described.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: A digital-to-analog conversion arrangement for converting a digital input signal comprises first and second digital-to-analog converters (DACs) having different signal resolutions and a digital-to-analog converter selector for selecting the first DAC or the second DAC if the digital input signal has a power in a first or a second power range, respectively. The digital-to-analog conversion arrangement further comprises an analog signal merger for merging a first analog signal and a second analog signal, the first analog signal being based on a first analog output signal of the first digital-to-analog converter and the second analog signal being based on a second analog output signal of the second analog-to-digital converter. A corresponding method for digital-to-analog conversion of a digital input signal and a computer readable digital storage medium are also described.

Abstract: A method for testing electronic devices involves receiving a stimulus signal for testing a device; changing an operating temperature of at least a component of an electrical filter while maintaining settings of the electrical filter, thereby altering the stimulus signal as the stimulus signal passes through the electrical filter, to create an altered stimulus signal; and outputting the altered stimulus signal.

Abstract: A high-frequency switching assembly having a first switching state and a second switching state includes a transmitter and a switch assembly. The transmitter includes a primary side and a secondary side having a first secondary side terminal and a second secondary side terminal and is configured to transmit an HF input signal applied to its primary side to its secondary side by means of inductive coupling. The switch assembly is configured to apply, in one state, a first reference potential to the first secondary side terminal. Further, the switch assembly is implemented to apply, in another state, a second reference potential to the second secondary side terminal.

Abstract: A system and method electronically tests devices. The method comprises receiving a first testing model including a first plurality of parameters and acceptable limits for the first plurality of parameters; receiving a second testing model including a second plurality of parameters and acceptable limits for the second plurality of parameters; receiving a first value for a first parameter from the first plurality of parameters, the first parameter at least partially affecting a second parameter from the second plurality of parameters; determining a second value for the second parameter based on the first value; determining if the first value is within the acceptable limits for the first parameter; determining if the second value is within the acceptable limits for the second parameter; and providing an indication when at least one of the first and second values is outside the acceptable limits for a corresponding one of the first and second parameters.

Abstract: A method for testing electronic devices comprises receiving a stimulus signal for testing a device. The method comprises setting a filter by changing a performance characteristic of the filter while maintaining settings of the filter, thereby altering the stimulus signal to create an altered stimulus signal. The method comprises outputting the altered stimulus signal.

Abstract: A coupler and associated method electronically tests devices. The method comprises receiving a stimulus signal for testing the electronic device, receiving an aggressor signal, injecting the aggressor signal into the stimulus signal to create a resultant signal that is the stimulus signal having a jitter, and sending the resultant signal to the electronic device. The coupler comprises an input port to receive a stimulus signal for testing the electronic device, an injection device to inject an aggressor signal into the stimulus signal to create a resultant signal that is the stimulus signal having a jitter, and an output port to output the resultant signal to the electronic device.

Abstract: Executing an allgather operation on a parallel computer that includes a plurality of compute nodes where the compute nodes are organized into at least one operational group of compute nodes for collective parallel operations of the parallel computer, and each compute node in the operational group is assigned a unique rank. In such a parallel computer, executing an allgather operation may include configuring on each compute node in an operational group of compute nodes a memory buffer with contribution data for an allreduce operation at a rank-dependent position in each memory buffer and zeros in all other positions in each memory buffer and executing on the compute nodes in the operational group, with the entire contents of each memory buffer, an allreduce operation with a bitwise OR function.

Abstract: A hybrid method of predicting the occurrence of future critical events in a computer cluster having a series of nodes records system performance parameters and the occurrence of past critical events. A data filter filters the logged to data to eliminate redundancies and decrease the data storage requirements of the system. Time-series models and rule based classification schemes are used to associate various system parameters with the past occurrence of critical events and predict the occurrence of future critical events. Ongoing processing jobs are migrated to nodes for which no critical events are predicted and future jobs are routed to more robust nodes.

Abstract: An oscillator circuit is specified, having an LC resonator, to which two or more current paths are connected, which are connected in parallel with one another and can be connected and disconnected individually by switches. The attenuation compensation amplifiers are in this case coupled to the resonant circuit in order to compensate for its attenuation. The oscillator circuit allows the gradient of the compensation for the attenuation of the resonant circuit to be adjusted, without moving the operating point of the amplifiers. This makes it possible to compensate for manufacturing-dependent component tolerances and any amplitude discrepancy caused by them, in a simple way. The oscillator circuit is suitable, for example, for use in voltage-controlled oscillators in order to form phase-locked loops when using mass production technologies.

Abstract: An oscillator circuit is specified, having an LC resonator, to which two or more current paths are connected, which are connected in parallel with one another and can be connected and disconnected individually by switches. The attenuation compensation amplifiers are in this case coupled to the resonant circuit in order to compensate for its attenuation. The oscillator circuit allows the gradient of the compensation for the attenuation of the resonant circuit to be adjusted, without moving the operating point of the amplifiers. This makes it possible to compensate for manufacturing-dependent component tolerances and any amplitude discrepancy caused by them, in a simple way. The oscillator circuit is suitable, for example, for use in voltage-controlled oscillators in order to form phase-locked loops when using mass production technologies.

Abstract: A checkpoint of a process is taken in order to provide a consistent state of the process in the event the process is to be restarted. When the process is restarted, the process is placed in the state it was in when the checkpoint was taken. However, there are times when certain information has changed since the last checkpoint and it should not be restored. For example, if a process is restarted on a computing unit different from the one in which the checkpoint is taken, then various attributes associated with external data referenced by the process (e.g., an address to an external function/variable) might be different than at the time of the checkpoint. Similarly, even on the same computing unit, if the functions and/or variables are reloaded, the attributes may be different. Since these new attribute values are needed for the restarted process, they should not be restored. In order to prevent restoration of the attributes, only part of the Data Section is restored.