Abstract: A bookmark memory stick includes a PC board, a flat, elongated insulative holder shell having a recessed accommodation portion accommodating the PC board and a retaining hole disposed near the top end thereof, a metal cover shell surrounding the insulative holder shell and a clip, which has a transverse locating base fitted into a locating notch at the top end of the insulative holder shell, a double-bevelled clamping plate obliquely downwardly extended from the front side of the transverse locating base toward the inside of the metal cover shell and stopped against a inverted T-plate of the insulative holder shell and then curved obliquely outwardly for clamping a sheet member on the inverted T-plate, a back plate extended from the back side of the transverse locating base and inserted into the inner top side of the metal cover shell, and a hook plate obliquely extended from the back plate and engaged into the retaining hole of the insulative holder shell.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: A side-push retractable USB memory stick includes a PC board providing a data storage function, an insulative PC board holder accommodating the PC board and having a springy plate located on one lateral side thereof and a press portion outwardly protruded from the springy plate, a housing surrounding the insulative PC board holder and having a sliding slot located on one lateral side thereof for receiving the press portion and enabling the press portion to be operated by an external force to move a metal shield and a USB interface circuit of the PC board in and out of a front opening of the housing. A rear end block closed on a rear open side of the housing, and a front end block press-fitted into the front opening and defining a through hole for passing the metal shield and the USB interface circuit in and out of the housing.

Abstract: A circuit comprises first and second differential pairs and first and second switch circuits. The first differential pair includes first and second transistors operable to generate a first output signal based on a first input signal in a single-ended mode. The second differential pair includes third and fourth transistors operable to generate a second output signal based on a second input signal in the single-ended mode. The first switch circuit is operable to block current through the second transistor in a differential mode. The second switch circuit is operable to block current through the third transistor in the differential mode. The first and the fourth transistors are operable to generate a third output signal based on a third input signal in the differential mode.

Abstract: Circuits and techniques for operating an integrated circuit (IC) with a configurable input-output circuit are disclosed. A disclosed circuit includes a single-ended input-output buffer coupled to an output terminal. The single-ended input-output buffer is operable to transmit an input signal to the output terminal as an output signal. A pre-emphasis circuit that is operable to sharpen a first edge and a second edge of the output signal is coupled between the single-ended input-output buffer and the output terminal. The first edge of the output signal is sharpened when the input signal switches from a first logic level to a second logic level while the second edge of the output signal is sharpened when the input signal switches from the second logic level to the first logic level.

Abstract: A memory stick having a lock device includes a metal housing, a PC board, a tray carrying the PC board, lock body, a lock body having a positioning block press-fitted into a top opening of the metal housing and a locating block engaged into a top notch of the metal housing and adapted for accommodating an upper part of the tray and a part of an IC package circuit of the PC board for enabling the USB interface circuit to be suspending in a bottom opening of the metal housing, and a locking mechanism for enabling the memory stick to be locked to an external object.

Abstract: A bookmark memory stick includes a PC board, a flat, elongated insulative holder shell having a recessed accommodation portion accommodating the PC board and a retaining hole disposed near the top end thereof, a metal cover shell surrounding the insulative holder shell and a clip, which has a transverse locating base fitted into a locating notch at the top end of the insulative holder shell, a double-bevelled clamping plate obliquely downwardly extended from the front side of the transverse locating base toward the inside of the metal cover shell and stopped against a inverted T-plate of the insulative holder shell and then curved obliquely outwardly for clamping a sheet member on the inverted T-plate, a back plate extended from the back side of the transverse locating base and inserted into the inner top side of the metal cover shell, and a hook plate obliquely extended from the back plate and engaged into the retaining hole of the insulative holder shell.

Abstract: A USB memory stick includes a metal shell structure defining opposing top opening and bottom opening and a locating hole, a PC board formed of a USB interface circuit and a memory chip package, and a tray, which includes a support panel supporting the PC board, a clip extended from one side of the support panel and clamped on the memory chip package of the PC board, a spring plate extended from the clip and pressed on the PC board against the support panel, and an oblique retaining leaf obliquely extended from the spring plate and engaged into the locating hole of the metal shell structure.

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

Abstract: An electrically conductive polymer compound is disclosed. The compound comprises a matrix comprising two polyolefin copolymers having different melt mass flow rates and electrically conductive functional additive particles dispersed in the matrix. The compound is useful for making extruded and molded plastic articles that need electrical conductivity.

Abstract: A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: A retractable USB memory stick includes a metal casing having a longitudinal sliding slot, first and second locating holes located on opposing ends of the longitudinal sliding slot and a hook located on the rear side and defining an access gap, a PC board having a USB plug and a memory IC board, and an insulation PC board holder holding the PC board and slidably mounted in the metal casing. The insulation PC board holder has a sliding block supported on a spring strip and inserted into the longitudinal sliding slot of the metal casing, retaining blocks protruded from the sliding block for selectively engaging the first locating hole or second locating hole to lock the insulation PC board holder to the metal casing in extended or received positions, and a latch located on the rear side and movable with the insulation PC board holder to close/open the access gap.

Abstract: A retractable USB memory stick includes a metal casing formed of a seamless flat tube having opposing front opening and rear opening, a sliding slot located on one peripheral wall thereof, and first and second locating holes located on the sliding slot, a PC board having a front USB interface circuit and a rear memory IC package, and an insulation PC board holder holding the PC board and slidably mounted in the metal casing. The insulation PC board holder has a spring strip bridged on the outside wall thereof, a sliding block located on the spring strip and forced by the spring power of the spring strip into the sliding slot of the metal casing, and a retaining block protruded from the sliding block for selectively engaging the first locating hole or second locating hole of the metal casing to lock the insulation PC board holder to the metal casing in the extended position and received position.

Abstract: A memory stick includes a -shaped metal plate member having two tenones respectively protruded from an inner wall thereof at two opposite sides and aimed at each other, each tenon being formed on the -shaped metal plate member by means of punching the inner wall of the -shaped metal plate member with a punch to form a protrusion and then punching the protrusion with a punch rod to extend the height of the protrusion and to deform the protrusion into a tubular configuration, and a casing accommodating a PC board that has a USB connector at its one end and having two pivot holders symmetrically located on two opposite sides thereof and respectively pivotally coupled to the tenones of the -shaped metal plate member for enabling the -shaped metal plate member to be turned relative to the casing to close or open the USB connector.

Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.

Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.