Patents by Inventor Joseph Siegel

Joseph Siegel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6785855
    Abstract: A system and method for implementing an assertion check in an ATPG scan cell is provided. The assertion check includes an error signal generator within a scan cell that generates an error signal when there is a violation of necessary conditions for testing the integrated circuit using APTG. According to the illustrative embodiment, the scan cell comprises a set-reset flip-flop paired with a latch. The flip-flop is used as a master storage element and the latch is used as a slave storage element to form a scan path. The master flip-flop and the slave latch are connected to form a shift register for shifting test data through the circuit under test. A system clock drives the standard operational mode of the storage elements and a shift clock drives the test mode. An enable clock is used to activate the system clock and switch the scan cell between the standard operational mode and the test mode.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: August 31, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Aiteen Zhang, Joseph Siegel
  • Publication number: 20030158697
    Abstract: A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.
    Type: Application
    Filed: February 19, 2002
    Publication date: August 21, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Spencer M. Gold, Claude R. Gauthier, Steven R. Boyle, Kenneth A. House, Joseph Siegel
  • Patent number: 6570407
    Abstract: A scannable latch for use within a circuit path of a series of one or more dynamic circuits is provided. The scannable latch provides both latch functionality during normal operation and scan test functionality during scan mode operation. Particularly, the scannable latch has a dynamic input stage and a shadow latch, where the dynamic input stage's primary function occurs during normal operations and where the shadow latch's primary function occurs during scan operations. The scannable latch also has an output gate operatively connected to the dynamic input stage and shadow latch.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: May 27, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Junji Sugisawa, Larry Kan, David Greenhill, Joseph Siegel
  • Publication number: 20030093734
    Abstract: A system and method for implementing an assertion check in an ATPG scan cell is provided. The assertion check includes an error signal generator within a scan cell that generates an error signal when there is a violation of necessary conditions for testing the integrated circuit using APTG. According to the illustrative embodiment, the scan cell comprises a set-reset flip-flop paired with a latch. The flip-flop is used as a master storage element and the latch is used as a slave storage element to form a scan path. The master flip-flop and the slave latch are connected to form a shift register for shifting test data through the circuit under test. A system clock drives the standard operational mode of the storage elements and a shift clock drives the test mode. An enable clock is used to activate the system clock and switch the scan cell between the standard operational mode and the test mode.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: Sun Microsystems, Inc., Palo Alto, CA
    Inventors: Aiteen Zhang, Joseph Siegel
  • Patent number: 6487702
    Abstract: A system and method for automatically selecting decoupling capacitors for an electronic device. The system determines a localized drive strength for each component in the electronic device. Based on a summation of drive strengths for components in a given area of the electronic device, the system determines whether a decoupling capacitor is necessary to provide local power bus stability.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: November 26, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Chen Li Lin, Joel Grinberg, Joseph Siegel
  • Publication number: 20020144217
    Abstract: A system and method for automatically selecting decoupling capacitors for an electronic device. The system determines a localized drive strength for each component in the electronic device. Based on a summation of drive strengths for components in a given area of the electronic device, the system determines whether a decoupling capacitor is necessary to provide local power bus stability.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 3, 2002
    Applicant: Sun Microsystems, Inc.
    Inventors: Chen Li Lin, Joel Grinberg, Joseph Siegel
  • Patent number: 3981028
    Abstract: An inner pocket is affixed to an outer pocket of an item in inverted position. The inner pocket has an open bottom spaced from and in close proximity with the bottom of the outer pocket. The inner pocket has a closed top in the outer area of the top of the outer pocket. Thus, an article is passable alongside the inner pocket in the pocket and into the inner pocket via the open bottom of the inner pocket and is inaccessible to casual removal from the outer pocket.
    Type: Grant
    Filed: June 9, 1975
    Date of Patent: September 21, 1976
    Assignee: The Raymond Lee Organization, Inc.
    Inventor: Joseph Siegel