Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.

Abstract: In various embodiments, a voltage collection bootstrap circuit includes a capacitor, an inductor, an oscillator, a bias circuit, and a switch. A current may be induced in the inductor, the oscillator, or both. The inductor, the oscillator, or both may store energy in the capacitor. The inductor, capacitor, and oscillator may supply energy to the bias circuit. The bias circuit may output a difference between a reference voltage and a voltage corresponding to the energy received from at least one of the inductor, capacitor, and oscillator. Based on the output of the bias circuit, a switch may connect the voltage collection circuit to an output of at least one of the inductor, capacitor, and oscillator. Accordingly, energy may be provided to the voltage collection circuit using one or more induced currents.

Abstract: In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

Abstract: An apparatus for determining an average current through an inductor of a regulator circuit is disclosed. A counter unit may be configured to receive a control signal, which includes a plurality of pulses, from a Power Management Unit (PMU), and determine a number of pulses received during a predetermined period of time. A pulse sampler unit may determine a duration of a given pulse of the plurality of pulses. Circuitry may be configured to determine the average current through the inductor during the predetermined period of time dependent upon the number of pulses received during the predetermined period of time and the duration of the given pulse.

Abstract: A method and apparats for undervoltage detection and correction is disclosed. An IC includes sensors implemented in various functional circuit blocks. The sensors are implemented using ring oscillators, and may be characterized by a polynomial. The sensors are used to monitor a supply voltage provided to a corresponding functional unit. The sensors provide information indicative of the voltage on the supply voltage node over successive clock cycles. Comparison circuitry may be used to compare the detected voltage to one or more voltage thresholds, while delta comparison circuitry may be used to determine a slope, or rate of change of the voltage. Based on comparisons performed by the comparison circuitry and the delta comparison circuitry, control circuitry may determine if one or more voltage correction actions are to be taken in order to bring the voltage on the supply node into a specified range.

Abstract: In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

Abstract: A method and apparats for undervoltage detection and correction is disclosed. An IC includes sensors implemented in various functional circuit blocks. The sensors are implemented using ring oscillators, and may be characterized by a polynomial. The sensors are used to monitor a supply voltage provided to a corresponding functional unit. The sensors provide information indicative of the voltage on the supply voltage node over successive clock cycles. Comparison circuitry may be used to compare the detected voltage to one or more voltage thresholds, while delta comparison circuitry may be used to determine a slope, or rate of change of the voltage. Based on comparisons performed by the comparison circuitry and the delta comparison circuitry, control circuitry may determine if one or more voltage correction actions are to be taken in order to bring the voltage on the supply node into a specified range.

Abstract: An apparatus for determining an average current through an inductor of a regulator circuit is disclosed. A counter unit may be configured to receive a control signal, which includes a plurality of pulses, from a Power Management Unit (PMU), and determine a number of pulses received during a predetermined period of time. A pulse sampler unit may determine a duration of a given pulse of the plurality of pulses. Circuitry may be configured to determine the average current through the inductor during the predetermined period of time dependent upon the number of pulses received during the predetermined period of time and the duration of the given pulse.

Abstract: In an embodiment, a supply voltage envelope detector circuit is configured to detect a shape of the supply voltage over time and to compare the detected shape to expected shapes that indicate voltage droop events for which corrective action may be needed. The expected shapes may be predetermined based on one or more of: the design of the integrated circuit that includes the supply voltage envelope detector circuit; attributes of the power management unit (PMU) that is to generate the supply voltage for the integrated circuit; and/or attributes of the system that includes the integrated circuit. The shape of the voltage droop may experience little variation during use, and thus may be used to detect a droop event earlier and more accurately than a threshold-based mechanism, in some embodiments.

Abstract: Disclosed is a switching voltage regulator circuitry controlled to supply a voltage to at least a portion of an integrated circuit (IC). Information corresponding to a current load for a different power state of at least a portion of the IC is received. The switching voltage regulator circuitry is controlled to adjust the voltage to a different value based at least in part on the received information. Disclosed is a voltage received for a power state of at least a portion of an IC having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the IC is sent from the second logic to voltage regulator control logic to adjust the voltage to a different value.

Abstract: In accordance with some embodiments, margining routines to determine acceptable voltage command values for specific CPU implementations at one or more different operating levels may be provided.

Abstract: In accordance with some embodiments, margining routines to determine acceptable voltage command values for specific CPU implementations at one or more different operating levels may be provided.

Abstract: Disclosed is a switching voltage regulator circuitry controlled to supply a voltage to at least a portion of an integrated circuit (IC). Information corresponding to a current load for a different power state of at least a portion of the IC is received. The switching voltage regulator circuitry is controlled to adjust the voltage to a different value based at least in part on the received information. Disclosed is a voltage received for a power state of at least a portion of an IC having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the IC is sent from the second logic to voltage regulator control logic to adjust the voltage to a different value.

Abstract: In some embodiments, the invention provides a higher efficiency, real-time platform power management architecture for computing platforms. A more direct power management architecture may be provided using integrated voltage regulators and in some embodiments, a direct power management interface (DPMI) as well. Integrated voltage regulators, such as in-silicon voltage regulators (ISVR) can be used to implement quicker, more highly responsive power state transitions.

Abstract: Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock signal is powered by at least one switching-type voltage regulator. When the functional block is about to require an increased level of power, the associated clock is provided to drive the at least one regulator switches overriding their normal drive signal, which has a lower frequency. Thus, the switches are driven at a higher frequency sufficiently prior to (e.g., just ahead of) the load change to reduce the amount of droop that would otherwise occur.

Abstract: Embodiments of an apparatus, system and method are described for dynamically time-interleaving supply voltage modulation to shape a power profile. An apparatus may comprise, for example, a power management module to monitor power information received from a plurality of devices and send a power control signal including delay information to each device having power information that exceeds a power threshold, the delay information comprising information for time-interleaving power usage among the devices having power information that exceeds the power threshold. Other embodiments are described and claimed.

Abstract: In some embodiments, the number of active cells in a multi-cell voltage regulator is controlled so that the current-per-active-cell approaches a predefined target or to be within an acceptable range so that the active cells operate with suitable efficiency.