Abstract: Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.

Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.

Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top-side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top-side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top-side of the chip interconnect bridge and the first and second integrated circuit chips.

Abstract: On a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator is pattered. On a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via (TSV).

Abstract: Embodiments of the present invention are directed to microchannels having varied critical dimensions for efficient cooling of semiconductor integrated circuit chip packages. In a non-limiting embodiment of the invention, a patterning stack is formed over a substrate. The patterning stack includes a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer. A manifold trench is formed in a first region of the substrate and is recessed below a surface of the etch transfer layer. A microchannel trench is formed in a second region of the substrate to expose the surface of the etch transfer layer. The manifold trench and the microchannel trench are recessed such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer. A manifold and a microchannel are formed in the substrate by pattern transfer.

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

Abstract: A semiconductor wafer includes a first substrate and a first etch stop layer formed on the first substrate. The etch stop layer has an opening. The semiconductor wafer further includes a second substrate and a second etch stop layer formed on the second substrate. The first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate. A trench is formed in the opening.

Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.

Abstract: Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.

Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top-side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top-side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top-side of the chip interconnect bridge and the first and second integrated circuit chips.

Abstract: Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.

Abstract: A semiconductor device includes a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple, including a bottom tier including a contact disposed on a first inverter gate, a top tier including a second inverter gate, and a monolithic inter-tier via (MIV) that lands on the contact via the second inverter gate.

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

Abstract: A semiconductor device includes a base structure including contacts and a first interlevel dielectric (ILD) layer, a metal-insulator metal (MIM) capacitor structure on the base structure, a second ILD layer on the MIM capacitor structure, and a plurality of vias penetrating through the first and second ILD layers to respective ones of the contacts.

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.

Abstract: A semiconductor wafer includes a first substrate and a first etch stop layer formed on the first substrate. The etch stop layer has an opening. The semiconductor wafer further includes a second substrate and a second etch stop layer formed on the second substrate. The first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate. A trench is formed in the opening.

Abstract: Embodiments of the present invention are directed to microchannels having varied critical dimensions for efficient cooling of semiconductor integrated circuit chip packages. In a non-limiting embodiment of the invention, a patterning stack is formed over a substrate. The patterning stack includes a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer. A manifold trench is formed in a first region of the substrate and is recessed below a surface of the etch transfer layer. A microchannel trench is formed in a second region of the substrate to expose the surface of the etch transfer layer. The manifold trench and the microchannel trench are recessed such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer. A manifold and a microchannel are formed in the substrate by pattern transfer.