Abstract: Structures and methods that facilitate forming isolated contacts in stacked vertical transport field effect transistors (VTFETs). A pair of stacked VTFETs are formed on a substrate and isolated from each other. A via or hole is formed to extend to a drain of the second VTFET and a source of the first VTFET. The via is filled with a metal below the first VTFET to form the second contact. The second contact is capped with a non-conductive material and the remaining portion of the via is filled with metal to form the first contact. Alternatively, a via or hole is formed to extend to a source of the second VTFET and a source of the first VTFET. The second contact may serve as a local interconnect, a ground, or a voltage source connection.

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

Abstract: On a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator is pattered. On a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via (TSV).

Abstract: Structures and methods that facilitate forming isolated contacts in stacked vertical transport field effect transistors (VTFETs). A pair of stacked VTFETs are formed on a substrate and isolated from each other. A via or hole is formed to extend to a drain of the second VTFET and a source of the first VTFET. The via is filled with a metal below the first VTFET to form the second contact. The second contact is capped with a non-conductive material and the remaining portion of the via is filled with metal to form the first contact. Alternatively, a via or hole is formed to extend to a source of the second VTFET and a source of the first VTFET. The second contact may serve as a local interconnect, a ground, or a voltage source connection.

Abstract: Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device.

Abstract: A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure including one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower VTFET, an isolation layer, and a second semiconductor layer providing a vertical transport channel for an upper VTFET. The method also includes forming at least one vertical via in the stacked VTFET structure spaced apart from the one or more vertical fins. The method further includes forming at least one horizontal via extending from the vertical via to at least one source/drain region of at least one of the upper and lower VTFETs. The method further includes forming a contact liner in the horizontal via, forming a barrier layer on sidewalls of the vertical via and the contact liner, and forming a contact material over the barrier layer in the vertical via.

Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.

Abstract: Devices and methods are provided for fabricating metallic interlayer via contacts within source/drain regions of field-effect transistor devices of a monolithic three-dimensional semiconductor integrated circuit device. For example, a semiconductor integrated circuit device includes a first device layer and a second device layer disposed on the first device layer. The first device layer includes a metallic interconnect structure formed in an insulating layer. The second device layer includes first and second field-effect transistor devices having respective first and second gate structures. A metallic interlayer via contact is disposed between the first and second gate structures in contact with the metallic interconnect structure of the first device layer, wherein a width of the metallic interlayer via contact is defined by a spacing between adjacent sidewalls of the first and second gate structures.

Abstract: A method for forming contacts on a semiconductor device includes depositing conductive material in one or more trenches and over an etch stop layer to a height above the etch stop layer, patterning a resist on the conductive material with shapes over one or more source/drain regions in the one or more trenches, and forming one or more trench lines in the one or more trenches and one or more self-aligned contacts below the shapes, including subtractively etching the conductive material to remove the conductive material from over the etch stop layer and to recess the conductive material into the one or more trenches without the shapes.

Abstract: Devices and methods are provided for fabricating a metal-insulator-metal capacitor within an interconnect structure (e.g., back-end-of-line interconnect structure) to provide capacitive decoupling between positive and negative power supply voltage lines of a power distribution network. Various via contact configurations including interlevel via contacts and truncated via contacts are utilized to connect the metal-insulator-metal capacitor electrodes to power supply voltage lines of the power distribution network to provide an array of high-density, low resistance via contact connections at various locations across the capacitor electrodes to reduce the resistance of the metal-insulator-metal capacitor and, thus, enhance the transient response time and increase the cutoff frequency of the metal-insulator-metal capacitor.

Abstract: Devices and methods are provided for fabricating a metal-insulator-metal capacitor within an interconnect structure (e.g., back-end-of-line interconnect structure) to provide capacitive decoupling between positive and negative power supply voltage lines of a power distribution network. Various via contact configurations including interlevel via contacts and truncated via contacts are utilized to connect the metal-insulator-metal capacitor electrodes to power supply voltage lines of the power distribution network to provide an array of high-density, low resistance via contact connections at various locations across the capacitor electrodes to reduce the resistance of the metal-insulator-metal capacitor and, thus, enhance the transient response time and increase the cutoff frequency of the metal-insulator-metal capacitor.

Abstract: A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the plurality of fins. A sacrificial gate material is deposited on and around the plurality of fins. First trenches are formed in the sacrificial gate material. The first trenches extend through the oxide layer to a top surface of the substrate and are arranged between fins of the plurality of fin. First trenches are filled with a metal gate stack. Second trenches are formed in the sacrificial gate material, with a bottom surface of the second trenches being arranged over a bottom surface of the first trenches, and the second trenches being arranged between fins of the plurality of fins and alternating with the first trenches. The second trenches are filled with a metal gate stack.

Abstract: Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device.

Abstract: A vertical transport field-effect transistor architecture is fabricated using a fin-last fabrication technique that enables pre-patterning of sacrificial gate layers and/or sacrificial source/drain layers with substantially flat topography prior to fin formation. Fins are epitaxially grown in trenches extending vertically through the device layers. Discrete regions of the sacrificial layers are later removed and replaced with appropriate source/drain and/or gate materials. Dielectric spacer elements are used to constrain feature dimensions of the replacement materials.

Abstract: Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins.

Abstract: A semiconductor device includes a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple, including a bottom tier including a contact disposed on a first inverter gate, a top tier including a second inverter gate, and a monolithic inter-tier via (MIV) that lands on the contact via the second inverter gate.

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

Abstract: Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device.

Abstract: Devices and methods are provided for fabricating metallic interlayer via contacts within source/drain regions of field-effect transistor devices of a monolithic three-dimensional semiconductor integrated circuit device. For example, a semiconductor integrated circuit device includes a first device layer and a second device layer disposed on the first device layer. The first device layer includes a metallic interconnect structure formed in an insulating layer. The second device layer includes first and second field-effect transistor devices having respective first and second gate structures. A metallic interlayer via contact is disposed between the first and second gate structures in contact with the metallic interconnect structure of the first device layer, wherein a width of the metallic interlayer via contact is defined by a spacing between adjacent sidewalls of the first and second gate structures.