Patents by Inventor Josuke Nakata

Josuke Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6153007
    Abstract: The present invention relates to a manufacturing method for a monocrystal and to a monocrystal manufacturing device. The present invention relates to a technology for manufacturing a granular monocrystal, wherein: melt of melted raw material is made into a supercooled spherical melt; while the melt is levitated under microgravitational conditions, the free energy of a portion of the surface of the melt is reduced, and a monocrystal is grown. A monocrystal manufacturing device 31 comprises: a gold image furnace 35, a chamber 33, a raw material supply/retention mechanism 38; a drop tube 36 and a drop tube 37; a rotating plate 39; a recovery vat 40; and the like. Raw material 32a of semiconductor material is heated and melted and allowed to free fall in a vacuum inside drop tubes 36, 37. During the drop, rotating plate 39 comes into contact with a portion of the surface of supercooled spherical melt 32b, and a crystal nucleus is generated.
    Type: Grant
    Filed: June 22, 1999
    Date of Patent: November 28, 2000
    Inventor: Josuke Nakata
  • Patent number: 5817173
    Abstract: The present invention relates to a method for forming crystal substrates on which can be easily formed spherical crystals which have superior crystal structure and little defect in shape. The present invention also relates to a method for making crystal substrates on which can be easily formed spherical crystals which have little defect in shape and from which impurities have been removed. Projections are formed integrally from a semiconductor crystal base, and flow regulating film is formed to cover the entire outer surface of the crystal base and a base portion of the projections. A heating beam is applied to the tips of the projections, and the end portions of the projections are melted. The surface tension of the melt and the melt regulation by the flow regulating film act to solidify the melt in a spherical shape, thus forming a spherical crystal.
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: October 6, 1998
    Inventor: Josuke Nakata
  • Patent number: 5785768
    Abstract: A photo cell and a photo cell array which have high photoelectric conversion efficiency, little leakage current, long life, and high reliability, as well as a electrolytic device that employs the cell and array. The photo cell (1) comprises: a base material (2) consisting of p-type semiconductor; a light receiving section (3) being an integral spherical part of the base material (2) which protrudes outward from the surface of the base (2), and has an n-type semiconductor layer formed on the surface of said spherical part, so that a pn junction interface is formed between the base material (2) and the semiconductor layer; a front surface electrode (4) formed from conductive material in ohmic contact with a portion of the surface of the aforementioned sphere; and a lower or back electrode (5) formed from conductive material on the bottom of the aforementioned base material (2), to provide ohmic contact.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: July 28, 1998
    Inventor: Josuke Nakata
  • Patent number: 4210466
    Abstract: A process for preparing heat sensitive semiconductor switch which switches from OFF state to ON state at relatively low temperature.In a heat sensitive thyristor having PNPN four layer structure, an N type base region is exposed at one part of the surface exposed part in the P type base region to form an opening and ions of a P type impurity such as boron, aluminum and gallium are implanted from the opening to form a part having a large leakage current in a collector junction under excellent control, and to provide lower switching temperature for switching from the OFF state to the ON state with high reproducibility.
    Type: Grant
    Filed: December 5, 1978
    Date of Patent: July 1, 1980
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Mihashi, Josuke Nakata
  • Patent number: 4196361
    Abstract: A temperature change detector comprising a heat sensitive semiconductor switching device (heat sensitive thyristor) and which switches when a temperature of an element whose temperature is to be detected is changed by a specific value with respect to the ambient temperature.A variable impedance element such as a thermistor or a diode whose resistance is varied depending upon the ambient temperature is connected between the P gate terminal and the cathode terminal of the heat sensitive thyristor which is thermally coupled to the element whose temperature is to be detected, whereby the effect of the ambient temperature on the switching temperature characteristic of the heat sensitive thyristor is compensated.
    Type: Grant
    Filed: August 8, 1977
    Date of Patent: April 1, 1980
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Josuke Nakata
  • Patent number: 4152711
    Abstract: A p type semiconductor gate layer is buried in an N type semiconductor cathode layer to encircle a channel through which the forward current of a luminescent PN junction passes. A reverse voltage is applied to the gate layer to spread a depletion layer in the channel to control the forward current and therefore the emission of light. The gate layer may be disposed on that surface of the cathode layer remote from the luminescent PN junction with a groove disposed the other surface of the cathode layer to narrow the channel.
    Type: Grant
    Filed: March 25, 1977
    Date of Patent: May 1, 1979
    Assignee: Mitsubishi Denki Kabuchiki Kaisha
    Inventor: Josuke Nakata
  • Patent number: 4151011
    Abstract: A planar pnpn thyristor structure is prepared to include an SiO.sub.2 film with a thickness of about 10,000A wholly disposed on its main face to which pn junctions are exposed. That portion of the SiO.sub.2 film underlaid with an exposed edge of a collector junction and its adjacent portion are replaced by another SiO.sub.2 film about 1,000A thick. Then argon ions Ar.sup.+ with an implantation energy of 200 KeV are implanted into the thyristor structure through both films to permit a low lifetime region including a large number of lattice defects to be formed only in its main face portion overlaid with the thin SiO.sub.2 film resulting in a semiconductor thermally sensitive switching element effecting the switchover at a sufficiently low temperature.
    Type: Grant
    Filed: July 14, 1978
    Date of Patent: April 24, 1979
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Mihashi, Josuke Nakata, Toshio Sogo, Kenichi Yamanaka
  • Patent number: 4142115
    Abstract: This invention relates to a semiconductor device having as a part thereof a second semiconductor device to protect the first or main device against overheating and current overloads.
    Type: Grant
    Filed: December 9, 1976
    Date of Patent: February 27, 1979
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Josuke Nakata, Tohru Kameda
  • Patent number: 4127792
    Abstract: A monolithic semiconductor luminescent display device has p.sup.+ layers disposed in seven rows and five columns on one of the main faces of an n substrate to form discrete luminescent junctions between them, five anodes disposed on the p.sup.+ layers one for each column and provided with light emitting windows above the junctions, and a cathode disposed on the other main face of the substrate. Seven p.sup.+ control bands extend through the substrate along the rows respectively and include current passageways below the junctions. The passageways have cross sectional areas controlled with reverse voltages applied to the p.sup.+ bands through the gate electrodes respectively.
    Type: Grant
    Filed: May 27, 1977
    Date of Patent: November 28, 1978
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Josuke Nakata
  • Patent number: 4117505
    Abstract: A heat sensitive switching device comprises at least three pn junctions between a pair of main electrodes to change from the OFF state to the ON state under rising temperature in at least one quadrant of the main voltage - main current characteristic curve wherein a region for shortening the life-time of carriers is formed at a part of the pn junction which causes the reverse bias in the OFF state.
    Type: Grant
    Filed: November 19, 1976
    Date of Patent: September 26, 1978
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Josuke Nakata
  • Patent number: 4081818
    Abstract: A semiconductor heat sensitive switching device comprisesA first semiconductor layer having the first conductive type;A second semiconductor layer having the second conductive type for forming the first emitter PN junction which is disposed in the first semiconductor layer to be substantially parallel of one main surface to the bottom surface and to contact them at the end; andA third semiconductor layer having the second conductive type for forming the collector PN junction which is disposed in the first semiconductor layer with a space to the second semiconductor layer to be substantially parallel of one main surface to the bottom surface and to contact them at the end, and a high thermal carrier generation rate region which is formed in the depletion layer region of the bottom surface of the third semiconductor layer.
    Type: Grant
    Filed: October 14, 1976
    Date of Patent: March 28, 1978
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Josuke Nakata
  • Patent number: 4009059
    Abstract: A circular semiconductor wafer includes a thyristor surrounded by a diode through an annular V-shaped groove-filled with glass. That face of the wafer near to the extremity of the groove is disposed on a molybdenum plate through a brazing layer. A base layer on both faces of the wafer has those portions extending through the associated emitter region at predetermined positions to be exposed to the wafers face to form degenerate P-N junctions on and adjacent that face with the adjacent emitter portions. The brazing layer and the opposite electrode for the thyristor include small openings looking the exposed portions of the base layers and the adjacent emitter portions respectively.
    Type: Grant
    Filed: April 15, 1975
    Date of Patent: February 22, 1977
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Josuke Nakata
  • Patent number: 4009482
    Abstract: A thermally sensitive semiconductor switch structure has a nichrome strip vacuum evaporated and sintered in a zigzag pattern on a ceramic substrate and a silicon pellet disposed on the substrate through the nichrome strip and a glass layer. A thyristor is provided in the silicon pellet and is electrically insulated from the nichrome strip. The thyristor is adapted to be heated by a current flowing through the nichrome strip and to be turned on upon its reaching a predetermined temperature. When its temperature decreases below the predetermined magnitude, it is turned off.
    Type: Grant
    Filed: August 12, 1976
    Date of Patent: February 22, 1977
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Josuke Nakata
  • Patent number: 3979767
    Abstract: A semiconductor switching device is disclosed which includes a wafer comprising at least four semiconductive layers with adjacent layers being of opposite conductivity type to form a plurality of P-N junctions. At least part of the P-N junction between one outer layer of the four semiconductive layers and an adjacent layer is shunted by an additional layer formed in the wafer. The additional layer forms an electrical resistance path across the P-N junction, and is prepared by sintering or alloying a metal layer into the wafer material. A method of making the semiconductor switching device is also disclosed.
    Type: Grant
    Filed: September 20, 1973
    Date of Patent: September 7, 1976
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Josuke Nakata, Ryuji Denda
  • Patent number: 3972113
    Abstract: Boron is diffused into selected areas of each main face of an N silicon substrate and gallium is diffused into the entire main face to form a P-N junction including deeper portions alternating shallower portion. Selective etching is effected to form grooves in the shallower junction portions for dividing the P-N junction. Both main faces of the substrate except for the grooves are metallized and a passivation layer is applied to each groove. Alternatively, in order to form the P-N junction as above described, gallium is selectively diffused in the substrate followed by a further diffusion of the gallium.
    Type: Grant
    Filed: May 6, 1974
    Date of Patent: August 3, 1976
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Josuke Nakata, Takeshi Yamamoto, Hitoshi Matufuzi
  • Patent number: 3959621
    Abstract: A main thyristor is serially connected to a load across an AC source. A thermally sensitive thyristor is connected at the anode to the anode of the main thyristor through a resistor and at the cathode to the gate electrode of the main thyristor and responds to an ambient temperature exceeding a predetermined magnitude to be conducting. When conducting, the thyristor switches the main thyristor to its ON state. Alternatively, the anode of the thyristor may be connected to the junction of two series resistors connected across the anode and cathode of the main thyristor. The conducting thyristor turns the main thyristor off.
    Type: Grant
    Filed: September 16, 1974
    Date of Patent: May 25, 1976
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Josuke Nakata
  • Patent number: 3936328
    Abstract: A cylindrical substrate of semiconductive material is repeatedly incised by a saw to be formed with many parallel grooves while it has one portion of the peripheral portion remaining uncut throughout its length. Thus, the grooves define between them many parallel wafer units integrally interconnected through the uncut portion. Then all the wafer units are simultaneously cleaned, diffused with an impurity, etched, and so on. After the completion of all the simultaneous processing operations, the wafer units are removed from the uncut portion to form separate wafers.
    Type: Grant
    Filed: October 15, 1974
    Date of Patent: February 3, 1976
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Josuke Nakata