Abstract: A method of forming a gate oxide layer according to the invention is disclosed. In the method, a furnace or rapid thermal oxidation (RTO) chamber where a semiconductor substrate having a native oxide layer formed thereon is located is supplied with a high-temperature hydrogen gas to deoxidize the native oxide layer. Then, a gate oxide layer is formed over the semiconductor substrate. The semiconductor substrate having the gate oxide layer formed thereon is transferred through a vacuum transmission system into a reaction chamber where a polysilicon layer is formed on the gate oxide layer. Thus, the semiconductor substrate can avoid exposure to an oxygen-containing atmosphere to re-form a native oxide layer thereon.

Abstract: A method is described. A substrate is provided. A first conductive layer with a first width and a second conductive layer with a second width are formed on the substrate. Photolithography and etching processes are performed on the dielectric layer to at least expose a first region of the first conductive layer and a second region of the second conductive layer. An oxide layer is then formed over the dielectric layer and the exposed first and second conductive layers. The method of applying partial reverse mask is able to resolve the adhesion problem of the dielectric layer with low dielectric constant.

Abstract: The present invention relates to a method for preventing an electrostatic chuck positioned at the bottom of a plasma vacuum chamber from being corroded during a cleaning process. The electrostatic chuck comprises a conductive substrate functioned as a lower electrode in a plasma process, and an insulating layer on the conductive substrate to electrically isolate the semiconductor wafer and the conductive substrate. The cleaning process involves a plasma process in which a fluorine-contained gas is injected into the plasma vacuum chamber to remove the chemical layer on the inner wall of the plasma vacuum chamber. A ceramic shutter made of SiC material is reposed on the electrostatic chuck and a high DC voltage is applied to the conductive substrate and the ceramic shutter which causes the ceramic shutter and the electrostatic chuck tightly stick together due to an electrostatic reaction.

Abstract: A method of manufacturing a binary phase shift photomask. A phase shift layer and a mask layer are sequentially formed over a transparent substrate. The mask layer and the phase shift layer are patterned to form a plurality of first openings and a plurality of second openings that expose a portion of the transparent substrate. The mask layer is patterned to form a layer of mask material around the edges of the first openings. All first openings occupy an area greater than a preset minimum area while all second openings occupy an area greater than the preset minimum area. The mask layer only surrounds the first openings while the phase shift layer surrounds both the first and the second openings.

Abstract: A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.

Abstract: The present invention relates to a method for removing a first dielectric layer of a semiconductor wafer. The first dielectric layer is formed on the surface of a second dielectric layer of the semiconductor wafer. The method comprises performing a chemical mechanical polishing (CMP) process on the first dielectric layer to remove a predetermined thickness of the first dielectric layer, measuring the remaining thickness of the first dielectric layer, providing an etching table having a plurality of thickness ranges of the remaining first dielectric layer and corresponding etching back procedure or parameters of each of the thickness ranges, and performing an etching back process to horizontally remove the remaining first dielectric layer according to the etching back procedure or parameters of the thickness range corresponding to the measured thickness of the remaining first dielectric layer.

Abstract: A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.

Abstract: A method for chemical mechanical polishing a component includes providing an oxide layer and forming at least one via through the oxide layer. A tungsten layer is formed within the via and over the oxide layer. A first chemical mechanical polishing step is carried out on a polishing pad using a first slurry having an oxidizing component and having a pH of approximately 2 to approximately 4 to remove the tungsten layer from over the oxide layer. A second chemical mechanical polishing step is carried out on the polishing pad using a second slurry having a pH of approximately 2 to approximately 4 to polish scratches out of the oxide layer.

Abstract: A method of fabricating a dual damascene is provided. A dielectric layer is formed on a substrate. A diffusion barrier layer is formed on the dielectric layer. A portion of the diffusion barrier layer and the dielectric layer is removed to form a trench and a via hole. A barrier layer is formed on the diffusion barrier layer and in the trench and the via hole. The barrier layer on the diffusion barrier layer is removed by chemical-mechanical polishing. A conductive layer is formed in the trench and the via hole by selective deposition. A planarization step is performed with the diffusion barrier layer serving as a stop layer.

Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.

Abstract: A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.

Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.

Abstract: A fabrication equipment to form an opening plug is provided. The equipment at least includes a load/unload chamber, a degas chamber, an usual sputtering chamber, a radio frequency (RF) sputtering chamber, a physical vapor deposition (PVD) chamber, and a chemical vapor deposition (CVD). The load/unload chamber is used to load a substrate. The degas chamber is used to remove moisture on the substrate. The usual sputtering chamber is used to form an opening on the substrate. The PVD chamber is used to form a first glue layer. The RF sputtering chamber is used to remove an overhang structure on the first glue layer. The CVD chamber is used to form a second glue layer over the first glue layer.

Abstract: A method for forming a gate on a substrate for manufacturing semiconductor devices is described. The present method comprises the step of providing a gate oxide layer on top of a substrate. A polysilicon layer is overlaid on the gate oxide layer and then, a amorphous silicon layer is formed thereon. The stack of amorphous and polysilicon layers is defined to form a gate structure on gate oxide layer. Next, a thermal treatment is performed on the gate structure.

Abstract: A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.

Abstract: The present invention relates to a method for forming excellent conformity due to improved surface sensitivity. A substrate is providing on which a transistor is formed. Moreover, a blanket first dielectric layer is deposited over the substrate. Then, a first photoresist layer is formed over the dielectric layer, wherein the first photoresist layer is defined and etched to form a contact opening. Further, a first conductive layer is formed to fill the contact opening, and performing an etching process to remove the first conductive layer to form a node contact. Consequentially, a second conductive layer is deposited over the first dielectric layer and the node contact. A second photoresist layer is formed over the second conductive layer, wherein the second photoresist layer is defined and etched to form a storage node as an upper electrode of a capacitor. Next, a hemispherical silicon grain (HSG) is formed over and on a sidewall of the second conductive layer.

Abstract: A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias is applied. An argon flow with a high speed of etching/deposition is provided to form a second oxide layer. While forming the second oxide layer a triangular or trapezium profile is formed due to an etching effect to the corner. An argon flow with a low speed of etching/deposition is provided to form a third oxide layer. The gap filling is completed.

Abstract: A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.

Abstract: A method of forming a DRAM capacitor. A hemispherical grain structure is formed on the surface of the bottom electrode of the capacitor. By employing an additional annealing under a dopant contained ambient, the dopant is diffused into the hemispherical grain structure and distributed at the surface area of the hemispherical grain region.

Abstract: A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.