Abstract: A method for enhancing adhesion ability between copper and silicon nitride is disclosed. The present method comprises following steps: first, provide a substrate and then form a copper layer on the substrate; second, form a copper phosphide layer on the copper layer; and finally, form a silicon nitride layer on the copper phosphide layer. Herein, the copper phosphide layer is formed by a plasma enhanced chemical vapor deposition process. Therefore, any copper oxide layer that covers copper layer is replaced by the silicon phosphide layer and then adhesion between copper and silicon nitride is improved. Moreover, the silicon phosphide comprises two advantages: low resistance than copper oxide and efficiently prevent copper diffuses into surrounding dielectric layer.

Abstract: A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A semiconductor fabrication method is provided for fabricating a dual damascene structure in a semiconductor device. By this method, a dielectric layer is first formed over a semiconductor substrate, and then a void structure including a via hole and a trench is formed in the dielectric layer. Next, a metallization structure is formed in the void structure in the dielectric layer, and after this, a special etching agent is used to treat the exposed surface of the metallization structure so as to make the exposed surface substantially rugged. Finally, a passivation layer is formed over the metallization structure, with the metallization structure serving as the intended dual damascene structure.

Abstract: The present invention provides a cleaning solution for cleaning a polishing pad used in a chemical-mechanical polishing (CMP) process for polishing the surface of a semiconductor wafer. The cleaning solution comprises a potassium hydroxide (KOH) solution for cleaning off slurry remaining on the surface of the polishing pad, and a hydrogen peroxide (H.sub.2 O.sub.2) solution and ammonia water (NH.sub.4 OH) solution for removing abrasive debris remaining on the surface of the polishing pad after the chemical-mechanical polishing process.

Abstract: A method of fabricating shallow trench isolation (STI) forms a trench in a substrate and a liner oxide layer in the trench. A first high density plasma chemical vapor deposition (HDPCVD) is performed to form a conformal oxide layer on the liner oxide layer, without applying bias to the substrate. A second HDPCVD is then performed to form an oxide layer that fills the trench and covers the conformal oxide layer on the conformal oxide layer.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A physical vapor deposition device comprises a vacuum chamber in which Ar ions are generated, a wafer chuck for holding a circular-shaped semiconductor wafer, a circular-shaped metal target above the wafer, an annular metal coil between the metal target and the wafer and made of the same material as the metal target, and a voltage controller for supplying voltage to the metal target, the wafer chuck and the metal coil. During a PVD processing, the voltage controller generates voltage biases between the metal target and the wafer chuck and between the metal coil and wafer chuck. That causes Ar ions to bombard the metal target to release metal atoms sputtering onto the center portion of the wafer, and causes Ar ions to bombard the metal coil to release the metal atoms sputtering onto the peripheral portion of the wafer so as to create a uniform metal layer on the wafer.

Abstract: A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.

Abstract: An apparatus for controlling a uniformity of a polished material is described. An air bag comprises a plurality of tubular rings. An air-bag manifold controller is connected to the tubular rings. The air-bag manifold controller controls inflation and deflation of the tubular rings in order to draw up the polished material and control pressure difference between different areas of the polished material.

Abstract: A chemical-mechanical polishing station for polishing wafers. The polishing station comprises a slurry supplier, a polishing pad capable of collecting the slurry, and a polishing head capable of rotating a wafer and lowering the wafer onto the polishing pad in contact with the polishing pad and the slurry during a polishing session. The polishing head further includes a retaining ring for positioning the wafer. The retaining ring houses a light-emitting device capable of shining a beam of light onto the slurry and a light sensor for picking up the beam of light reflected back from the slurry. The exact polishing end-point can be decided by analyzing signals obtained from the light sensor.

Abstract: A chemical mechanical polishing apparatus for controlling slurry distribution is disclosed. The slurry flowing through the mesh before transferring to the polishing pad, the mesh being used to distribute the slurry onto surface of the polishing pad. There are different netting densities over the mesh, achieving the purpose of controlling slurry distribution.

Abstract: A method of forming a shallow trench isolation structure includes etching a substrate to form a trench. Then, an oxide layer is deposited in the trench and over the substrate by using high-density plasma. The oxide layer is pointed since it is formed by high-density plasma chemical vapor deposition. A stop layer made of silicon nitride, silicon oxy-nitride or boron nitride is formed on the oxide layer. The hardness of the stop layer is higher than that of the oxide layer so the protuberance of the oxide layer will be first removed during chemical mechanical polishing.

Abstract: An in-situ CMP slurry mixing apparatus. The apparatus comprises a tubular main body and a plurality of tapered plugs. The tubular main body further comprises a plurality of first tubes with a first diameter, a plurality of second tubes with a second diameter. Each tapered plug is placed in each second tube, the tips of each tapered plug are pointed in the same direction, and the tips are each oriented opposite to a flowing direction of a CMP slurry. In addition, the second diameter is larger than the first diameter, and a diameter of the base of each tapered plug is larger than the first diameter but is smaller than the second diameter.

Abstract: A post-CMP wafer clean process. A post-CMP wafer is provided. A portion of particles and slurry are removed from the wafer by double side scrubber. The residual particles and slurry are then removed from the wafer in a solvent tank by magasonic and a solvent in the solvent tank includes an amine-based compound.

Abstract: A method for fabricating trench isolation structures using the reverse mask is described. The method of using a reverse mask to fabricate trench isolation structures includes providing a semiconductor substrate having a first trench and a second trench in the substrate. The first trench has a width smaller than a fixed value, while the second trench has a width larger than the fixed value, the fixed value being, for example, about 0.7 .mu.m. Thereafter, a conformal insulating layer is formed over the first trench and the second trench. Next, a reverse mask layer is formed over the conformal insulating layer, and then the reverse mask layer is patterned. The reverse mask layer is patterned selectively. For example, only the region directly above the second trench is covered by the reverse mask. The region directly above the first trench is exposed.

Abstract: A method for adjusting the amount of doped nitride ions in a dielectric layer so that the nitride ions form bonds with silicon to increase the quality of an oxide layer. The method comprises the step of providing a silicon substrate. Next, a rapid thermal oxidation or furnace oxidation method is used to form an oxide layer over the silicon substrate. Gaseous mixtures having different ratios of nitrogen monoxide, nitrous oxide or ammonia to oxygen are concocted and then allowed to react at different reacting temperatures for controlling the nitride concentration level in the oxide layer. The nitride-doped oxide layer not only can stop the penetration of boron ions, but can also provide a stabilizing effect on the oxide layer/silicon substrate interface without degradation of electrical property, thereby improving the quality of a transistor.

Abstract: A slurry filtration system for supplying a slurry to a polisher to perform a chemical mechanical polishing process. The system comprises a first three-way valve, to receive the slurry supplied from an external system; a slurry pump, to control the slurry flowing from the first three-way valve, and to maintain a circulating state of the slurry within the circulating system after the chemical mechanical polishing process comes to a stop; a slurry filter, to filter a plurality of large size particles in the slurry pumped from the slurry pump; a second three-way valve, to supply the slurry flowing from the filter to the polisher; and a transportation pipe, connecting between the first and the second three-way valves to transport the slurry from the second three-way valve back to the first three-way valve when the polishing process has stopped.

Abstract: An antenna effect monitor includes a transistor formed on a semiconductor substrate. The transistor gate is coupled to a doped polysilicon interconnect layer which is also coupled to an antenna effect monitoring unit. Several metal bonding pads float in an orderly fashion above the doped polysilicon interconnect layer without coupling with each other. Several small metal layers are formed in an orderly fashion above the doped polysilicon interconnect layer but are electrically coupled together by several via plugs in between. The top small metal layer is coupled to the top bonding pad. The bottom small metal layer is electrically coupled to the doped polysilicon interconnect layer. Then a passivation layer covers the substrate but leaves a pad opening to expose the top bonding pad.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation. A substrate having a plurality of active regions, including a large active region and a small active region, is provided. A silicon nitride layer is formed on the substrate. A shallow trench is formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trench is filled therewith. A partial reverse active mask is formed on the oxide layer, so that the oxide layer on a central part of the large active region is exposed. Whereas, the oxide layer on an edge part of the large active region and on the small active region are covered by the partial reverse active mask. The oxide layer is etched with the silicon nitride layer as a stop layer, using the partial reverse active mask as a mask. The oxide layer is planarized until the oxide layer within the shallow trench has a same level as the silicon nitride layer.