Patents by Inventor Jui-Ching Wu
Jui-Ching Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240117342Abstract: An construction method of an embryonic chromosome signal library is provided. The construction method comprises obtaining an embryo and performing whole-genome amplification and next-generation sequencing to obtain a first chromosome signal; mapping the first chromosome signal to a chromosome reference signal to obtain a second chromosome signal; dividing the second chromosome signal within a predetermined interval range to obtain a third chromosome signal; and performing a regression correction on the sequencing read count (RC) of the third chromosome signal to obtain an embryonic chromosome signal library. Furthermore, a detection method and system of embryonic chromosomes are also provided. Thereby, the information comparison of the embryo chromosome signal library is used to determine whether the pre-implantation embryo is abnormal or not to achieve pre-implantation chromosome screening of pre-implantation embryos.Type: ApplicationFiled: October 2, 2023Publication date: April 11, 2024Inventors: LI-JEN SU, SHAO-PING WENG, YU-YU YEN, LI-CHING WU, HUI-YIN CHIU, JUI-HUNG KAO
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Patent number: 11378894Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.Type: GrantFiled: October 28, 2019Date of Patent: July 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
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Patent number: 10976672Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: GrantFiled: April 29, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
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Patent number: 10685846Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.Type: GrantFiled: May 16, 2014Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chin Chien, Jui-Ching Wu, Shu-Hao Chang, Shang-Chieh Chien, Jen-Yang Chung, Kuo-Chang Kau, Jeng-Horng Chen
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Publication number: 20200064747Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.Type: ApplicationFiled: October 28, 2019Publication date: February 27, 2020Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
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Patent number: 10559171Abstract: An electronic system sharing power with doorbell includes two power contacts, an AC switch, a first AC/DC conversion circuit, a DC switch, an electronic device, and a doorbell-driving device. The first AC/DC conversion circuit receives an AC power via the power contacts and generates a DC power according to the AC power. In a normal state, the AC switch is off and the DC switch is on. Therefore, the electronic device is powered by the DC power. When the electronic device receives an enabling signal, the electronic device controls the AC switch to be on, to cause the voltage of the doorbell contacts to change from a low voltage to a high voltage. The doorbell-driving device detects the voltage of the doorbell contacts and supplies the power to a doorbell according to the detected voltage.Type: GrantFiled: June 1, 2017Date of Patent: February 11, 2020Assignee: CHICONY ELECTRONICS CO., LTD.Inventor: Jui-Ching Wu
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Patent number: 10459353Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.Type: GrantFiled: January 30, 2014Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
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Publication number: 20190250522Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Jui-Ching WU, Jeng-Horng CHEN, Chia-Chen CHEN, Shu-Hao CHANG, Shang-Chieh CHIEN, Ming-Chin CHIEN, Anthony YEN
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Patent number: 10274838Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: GrantFiled: May 22, 2013Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
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Patent number: 10067418Abstract: A method of removing particles from a surface of a reticle is disclosed. The reticle is placed in a carrier, a source gas is flowed into the carrier, and a plasma is generated within the carrier. Particles are then removed from a surface of the reticle using the generated plasma. A system of removing particles from a surface includes a carrier configured to house a reticle, a reticle stocker including the carrier, a power supply configured to apply a potential between an inner cover and an inner baseplate of the carrier, and a gas source configured to flow a gas into the carrier. A plasma may be generated within the carrier, and particles can be removed from a surface of the reticle using the generated plasma. An acoustic energy source configured to agitate at least one of the source gas and the generated plasma may be provided to facilitate particle removal using an agitated plasma.Type: GrantFiled: May 12, 2014Date of Patent: September 4, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Hao Chang, Chi-Lun Lu, Shang-Chieh Chien, Ming-Chin Chien, Jui-Ching Wu, Jeng-Horng Chen, Chieh-Jen Cheng, Chia-Chen Chen
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Publication number: 20180190083Abstract: An electronic system sharing power with doorbell includes two power contacts, an AC switch, a first AC/DC conversion circuit, a DC switch, an electronic device, and a doorbell-driving device. The first AC/DC conversion circuit receives an AC power via the power contacts and generates a DC power according to the AC power. In a normal state, the AC switch is off and the DC switch is on. Therefore, the electronic device is powered by the DC power. When the electronic device receives an enabling signal, the electronic device controls the AC switch to be on, to cause the voltage of the doorbell contacts to change from a low voltage to a high voltage. The doorbell-driving device detects the voltage of the doorbell contacts and supplies the power to a doorbell according to the detected voltage.Type: ApplicationFiled: June 1, 2017Publication date: July 5, 2018Inventor: Jui-Ching WU
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Patent number: 9665007Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.Type: GrantFiled: August 29, 2016Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
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Publication number: 20170052385Abstract: A lens focusing method includes the following steps. A holder is disposed on a printed circuit board, such that the holder surrounds an image sensor that is on the printed circuit board. A lens assembly is rotated to position in the holder through a first thread of the holder and a second thread of the lens assembly. A tilt of the holder is adjusted, such that an optic axis of the lens assembly is perpendicular to the image sensor. The lens assembly is rotated to move to a focal plane in a vertical direction through the first and second threads again.Type: ApplicationFiled: January 24, 2016Publication date: February 23, 2017Inventors: JUI-CHING WU, JIN-KAE JANG, TSUNG-YOU WANG
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Patent number: 9558944Abstract: A reticle for use in an extreme ultraviolet (euv) lithography tool includes a trench formed in the opaque border formed around the image field of the reticle. The trench is coated with an absorber material. The reticle is used in an euv lithography tool in conjunction with a reticle mask and the positioning of the reticle mask and the presence of the trench combine to prevent any divergent beams of radiation from reaching any undesired areas on the substrate being patterned. In this manner, only the exposure field of the substrate is exposed to the euv radiation. Pattern integrity in neighboring fields is maintained.Type: GrantFiled: May 20, 2015Date of Patent: January 31, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hao Hsu, Chia-Chen Chen, Jui-Ching Wu, Shang-Chieh Chien, Chia-Jen Chen, Chia-Ching Huang
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Publication number: 20160370705Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.Type: ApplicationFiled: August 29, 2016Publication date: December 22, 2016Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
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Patent number: 9429858Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.Type: GrantFiled: September 24, 2013Date of Patent: August 30, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
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Patent number: 9412632Abstract: A reticle pod includes an outer pod shell and an outer pod door disposed under the outer pod shell. The outer pod door has at least one gas control hole. A seal ring is disposed between the outer pod shell and the outer pod door. A valve is disposed in each gas control hole. The outer pod shell and the outer pod door are configured to form an enclosure space in order to store a reticle. The seal ring seals the gap between the outer pod shell and the outer pod door. The at least one valve is configured to control gas flow in and out of the enclosure space.Type: GrantFiled: October 25, 2012Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yen Lee, Jeng-Horng Cheng, Jui-Ching Wu
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Publication number: 20160054664Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: ApplicationFiled: May 22, 2013Publication date: February 25, 2016Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
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Patent number: 9229326Abstract: Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.Type: GrantFiled: March 14, 2014Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Cheng Lu, Shu-Hao Chang, Shinn-Sheng Yu, Jui-Ching Wu, Jeng-Horng Chen, Anthony Yen
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Publication number: 20150332922Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.Type: ApplicationFiled: May 16, 2014Publication date: November 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chin Chien, Jui-Ching Wu, Shu-Hao Chang, Shang-Chieh Chien, Jen-Yang Chaung, Kuo-Chang Kau, Jeng-Horng Chen