Patents by Inventor Jui-Ching Wu
Jui-Ching Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150323862Abstract: A method of removing particles from a surface of a reticle is disclosed. The reticle is placed in a carrier, a source gas is flowed into the carrier, and a plasma is generated within the carrier. Particles are then removed from a surface of the reticle using the generated plasma. A system of removing particles from a surface includes a carrier configured to house a reticle, a reticle stocker including the carrier, a power supply configured to apply a potential between an inner cover and an inner baseplate of the carrier, and a gas source configured to flow a gas into the carrier. A plasma may be generated within the carrier, and particles can be removed from a surface of the reticle using the generated plasma. An acoustic energy source configured to agitate at least one of the source gas and the generated plasma may be provided to facilitate particle removal using an agitated plasma.Type: ApplicationFiled: May 12, 2014Publication date: November 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Hao Chang, Chi-Lun Lu, Shang-Chieh Chien, Ming-Chin Chien, Jui-Ching Wu, Jeng-Horng Chen, Chieh-Jen Cheng, Chia-Chen Chen
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Patent number: 9159559Abstract: The present disclosure provides a method for forming resist patterns. The method includes providing a substrate; forming a material layer including a plurality of quenchers on the substrate; forming a resist layer on the material layer; exposing the resist layer; and developing the resist layer to form a structure featuring resist remaining layer on an upper surface of the material layer, and a plurality of resist features on the resist remaining layer to improve the yield of lithography process.Type: GrantFiled: July 18, 2013Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Jeng-Horng Chen, Anthony Yen
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Patent number: 9140987Abstract: A method of reducing resist outgassing for EUV lithography is disclosed. The method includes forming a material layer over a substrate wherein a top surface of the material layer contains a certain concentration of a quencher or a base. The method further includes forming a resist layer over the top surface of the material layer and exposing the resist layer to a EUV radiation for patterning. The quencher or the base underneath the resist layer acts to suppress resist outgassing during the EUV exposure. The material layer itself may serve as a hard mask layer or an anti-reflection layer for the patterning process, in addition to being the carrier of the quencher or the base. The method can be used in other types of lithography, such as e-beam lithography, for reducing resist outgassing.Type: GrantFiled: February 21, 2014Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Chieh Chien, Shu-Hao Chang, Hsiang-Yu Chou, Ming-Chin Chien, Jui-Ching Wu, Jeng-Horng Chen
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Publication number: 20150262836Abstract: Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: YEN-CHENG LU, SHU-HAO CHANG, SHINN-SHENG YU, JUI-CHING WU, JENG-HORNG CHEN, ANTHONY YEN
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Publication number: 20150255272Abstract: A reticle for use in an extreme ultraviolet (euv) lithography tool includes a trench formed in the opaque border formed around the image field of the reticle. The trench is coated with an absorber material. The reticle is used in an euv lithography tool in conjunction with a reticle mask and the positioning of the reticle mask and the presence of the trench combine to prevent any divergent beams of radiation from reaching any undesired areas on the substrate being patterned. In this manner, only the exposure field of the substrate is exposed to the euv radiation. Pattern integrity in neighboring fields is maintained.Type: ApplicationFiled: May 20, 2015Publication date: September 10, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao HSU, Chia-Chen CHEN, Jui-Ching WU, Shang-Chieh CHIEN, Chia-Jen CHEN, Chia-Ching HUANG
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Publication number: 20150241776Abstract: A method of reducing resist outgassing for EUV lithography is disclosed. The method includes forming a material layer over a substrate wherein a top surface of the material layer contains a certain concentration of a quencher or a base. The method further includes forming a resist layer over the top surface of the material layer and exposing the resist layer to a EUV radiation for patterning. The quencher or the base underneath the resist layer acts to suppress resist outgassing during the EUV exposure. The material layer itself may serve as a hard mask layer or an anti-reflection layer for the patterning process, in addition to being the carrier of the quencher or the base. The method can be used in other types of lithography, such as e-beam lithography, for reducing resist outgassing.Type: ApplicationFiled: February 21, 2014Publication date: August 27, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Chieh Chien, Shu-Hao Chang, Hsiang-Yu Chou, Ming-Chin Chien, Jui-Ching Wu, Jeng-Horng Chen
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Patent number: 9046776Abstract: A reticle for use in an extreme ultraviolet (euv) lithography tool includes a trench formed in the opaque border formed around the image field of the reticle. The trench is coated with an absorber material. The reticle is used in an euv lithography tool in conjunction with a reticle mask and the positioning of the reticle mask and the presence of the trench combine to prevent any divergent beams of radiation from reaching any undesired areas on the substrate being patterned. In this manner, only the exposure field of the substrate is exposed to the euv radiation. Pattern integrity in neighboring fields is maintained.Type: GrantFiled: February 4, 2013Date of Patent: June 2, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hao Hsu, Chia-Chen Chen, Jui-Ching Wu, Shang-Chieh Chien, Chia-Jen Chen, Chia-Ching Huang
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Publication number: 20150085264Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.Type: ApplicationFiled: September 24, 2013Publication date: March 26, 2015Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
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Publication number: 20140347644Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: ApplicationFiled: May 22, 2013Publication date: November 27, 2014Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
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Publication number: 20140268074Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.Type: ApplicationFiled: January 30, 2014Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
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Publication number: 20140256146Abstract: The present disclosure provides a method for forming resist patterns.Type: ApplicationFiled: July 18, 2013Publication date: September 11, 2014Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Jeng-Horng Chen, Anthony Yen
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Publication number: 20140218714Abstract: A reticle for use in an extreme ultraviolet (euv) lithography tool includes a trench formed in the opaque border formed around the image field of the reticle. The trench is coated with an absorber material. The reticle is used in an euv lithography tool in conjunction with a reticle mask and the positioning of the reticle mask and the presence of the trench combine to prevent any divergent beams of radiation from reaching any undesired areas on the substrate being patterned. In this manner, only the exposure field of the substrate is exposed to the euv radiation. Pattern integrity in neighboring fields is maintained.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao HSU, Chia-Chen CHEN, Jui-Ching WU, Shang-Chieh CHIEN, Chia-Jen CHEN, Chia-Ching HUANG
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Publication number: 20140116920Abstract: A reticle pod includes an outer pod shell and an outer pod door disposed under the outer pod shell. The outer pod door has at least one gas control hole. A seal ring is disposed between the outer pod shell and the outer pod door. A valve is disposed in each gas control hole. The outer pod shell and the outer pod door are configured to form an enclosure space in order to store a reticle. The seal ring seals the gap between the outer pod shell and the outer pod door. The at least one valve is configured to control gas flow in and out of the enclosure space.Type: ApplicationFiled: October 25, 2012Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Yen Lee, Jeng-Horng Cheng, Jui-Ching Wu
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Patent number: 8563231Abstract: Methods for forming a pattern in a lithography process for semiconductor wafer manufacturing are provided. In an example, a method includes forming a photoresist layer over a material layer; performing a first exposure process on the photoresist layer, thereby forming an exposed photoresist layer having soluble portions and unsoluble portions; treating the exposed photoresist layer, wherein the treating includes one of performing a second exposure process on the exposed photoresist layer and forming an adsorbing chemical layer over the exposed photoresist layer; and developing the exposed and treated photoresist layer to remove the soluble portions of the photoresist layer, wherein the unsoluble portions of the photoresist layer form a photoresist pattern that exposes portions of the material layer.Type: GrantFiled: September 22, 2011Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Wei Wang, Ko-Bin Kao, Wei-Liang Lin, Jui-Ching Wu, Chia-Hsiang Lin, Ai-Jen Jung
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Publication number: 20130075364Abstract: Methods for forming a pattern in a lithography process for semiconductor wafer manufacturing are provided. In an example, a method includes forming a photoresist layer over a material layer; performing a first exposure process on the photoresist layer, thereby forming an exposed photoresist layer having soluble portions and unsoluble portions; treating the exposed photoresist layer, wherein the treating includes one of performing a second exposure process on the exposed photoresist layer and forming an adsorbing chemical layer over the exposed photoresist layer; and developing the exposed and treated photoresist layer to remove the soluble portions of the photoresist layer, wherein the unsoluble portions of the photoresist layer form a photoresist pattern that exposes portions of the material layer.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Wei Wang, Ko-Bin Kao, Wei-Liang Lin, Jui-Ching Wu, Chia-Hsiang Lin, Ai-Jen Jung