Patents by Inventor Jui-Chung Lee
Jui-Chung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11991853Abstract: A clip for securing one or more cables associated with a computing device includes a baseplate, a first wall, and a second wall. The first wall and the second wall extend from the baseplate. The first wall has a first inward projection at a distal end thereof. The second wall has a second inward projection at a distal end thereof. The first wall is generally parallel to the second wall. The first wall and the second wall are spaced apart from each other by an interior space configured to receive the one or more cables. The first inward projection and the second inward projection aid in preventing the one or more cables from moving outside of the interior space.Type: GrantFiled: September 19, 2022Date of Patent: May 21, 2024Assignee: QUANTA COMPUTER INC.Inventors: Chao-Jung Chen, Chih-Wei Lin, Jui-Chung Lee, Hui-Ying Suk
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Publication number: 20240008212Abstract: A clip for securing one or more cables associated with a computing device includes a baseplate, a first wall, and a second wall. The first wall and the second wall extend from the baseplate. The first wall has a first inward projection at a distal end thereof. The second wall has a second inward projection at a distal end thereof. The first wall is generally parallel to the second wall. The first wall and the second wall are spaced apart from each other by an interior space configured to receive the one or more cables. The first inward projection and the second inward projection aid in preventing the one or more cables from moving outside of the interior space.Type: ApplicationFiled: September 19, 2022Publication date: January 4, 2024Inventors: Chao-Jung CHEN, Chih-Wei LIN, Jui-Chung LEE, Hui-Ying SUK
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Patent number: 11678439Abstract: A circuit board includes a substrate, a plurality of contacts disposed on a surface of the substrate, and a solder mask. The contacts have a plurality of plating regions and a metal layer on the plating regions, and the plating regions have at least two different sizes. The solder mask covers the surface of the substrate and covers edges of the plating regions, in which topmost surfaces of the contacts are below a top surface of the solder mask, and a gap between the topmost surfaces of the contacts and the top surface of the solder mask is larger than 0 ?m and is smaller than 5 ?m.Type: GrantFiled: February 25, 2022Date of Patent: June 13, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Pei-Chi Hu, Jui-Chung Lee, Chi-Wen Lin
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Publication number: 20220183162Abstract: A circuit board includes a substrate, a plurality of contacts disposed on a surface of the substrate, and a solder mask. The contacts have a plurality of plating regions and a metal layer on the plating regions, and the plating regions have at least two different sizes. The solder mask covers the surface of the substrate and covers edges of the plating regions, in which topmost surfaces of the contacts are below a top surface of the solder mask, and a gap between the topmost surfaces of the contacts and the top surface of the solder mask is larger than 0 ?m and is smaller than 5 ?m.Type: ApplicationFiled: February 25, 2022Publication date: June 9, 2022Inventors: Pei-Chi HU, Jui-Chung LEE, Chi-Wen LIN
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Publication number: 20220117093Abstract: A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.Type: ApplicationFiled: October 13, 2020Publication date: April 14, 2022Inventors: Pei-Chi HU, Jui-Chung LEE, Chi-Wen LIN
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Patent number: 11304310Abstract: A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.Type: GrantFiled: October 13, 2020Date of Patent: April 12, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Pei-Chi Hu, Jui-Chung Lee, Chi-Wen Lin
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Patent number: 8547233Abstract: An integrated circuit includes a thermal-effect unit and a processing unit. The thermal-effect unit generates an electrical energy and forms a temporary channel when experiencing a thermal cycle. The processing unit has a thermal-cycle number, and updates the thermal-cycle number through the temporary channel in response to the electrical energy.Type: GrantFiled: November 1, 2010Date of Patent: October 1, 2013Assignee: Macronix International Co., Ltd.Inventors: Jui-Chung Lee, Wen-Hung Tu, Guo-Zhen Huang
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Patent number: 8240549Abstract: A carrier tray as described herein includes a container having pockets for holding electrical components such as integrated circuits during manufacturing, and a device coupled to the container for tracking usage of the carrier tray into and out of process chambers used for performing particular processes on the electrical components carried therein. Stations and methods of using the carrier tray are also described herein.Type: GrantFiled: July 29, 2009Date of Patent: August 14, 2012Assignee: Macronix International Co., Ltd.Inventors: Jui-Chung Lee, Chun-Ming Ko, Lan-Ben Wang
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Patent number: 8133759Abstract: A leadframe includes a die paddle and leads, in which the back side of the die paddle has a fillister. The fillister defines a rim surrounding a recess, and the recess accommodates protrusion of fusible material. Also, a package includes such a leadframe. Also, a method for making a leadframe includes patterning a sheet of metal to form a die paddle and leads, and forming a fillister in the back side of the die paddle.Type: GrantFiled: April 28, 2009Date of Patent: March 13, 2012Assignee: Macronix International Co., Ltd.Inventors: Jui-Chung Lee, Po-Hsin Lin, Kun-Feng Lee
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Publication number: 20120051491Abstract: An integrated circuit includes a thermal-effect unit and a processing unit. The thermal-effect unit generates an electrical energy and forms a temporary channel when experiencing a thermal cycle. The processing unit has a thermal-cycle number, and updates the thermal-cycle number through the temporary channel in response to the electrical energy.Type: ApplicationFiled: November 1, 2010Publication date: March 1, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jui-Chung Lee, Wen-Hung Tu, Guo-Zhen Huang
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Publication number: 20110024326Abstract: A carrier tray as described herein includes a container having pockets for holding electrical components such as integrated circuits during manufacturing, and a device coupled to the container for tracking usage of the carrier tray into and out of process chambers used for performing particular processes on the electrical components carried therein. Stations and methods of using the carrier tray are also described herein.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Applicant: Macronix International Co., Ltd.Inventors: JUI-CHUNG LEE, CHUN-MING KO, LAN-BEN WANG
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Publication number: 20100270665Abstract: A leadframe includes a die paddle and leads, in which the back side of the die paddle has a fillister. The fillister defines a rim surrounding a recess, and the recess accommodates protrusion of fusible material. Also, a package includes such a leadframe. Also, a method for making a leadframe includes patterning a sheet of metal to form a die paddle and leads, and forming a fillister in the back side of the die paddle.Type: ApplicationFiled: April 28, 2009Publication date: October 28, 2010Inventors: Jui-Chung Lee, Po-Hsin Lin, Kun-Feng Lee
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Publication number: 20070018333Abstract: A semiconductor packaging device comprises a carrier having at least a cavity/a slot thereon, at least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second plating through holes therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads.Type: ApplicationFiled: September 7, 2006Publication date: January 25, 2007Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chen-Jung TSAI, Jui-Chung LEE, Chih-Wen LIN
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Patent number: 7122904Abstract: A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first via-conductor connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second via-conductor therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first via-conductor are electrically connected with the conductive layout lines, the second via-conductor, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls.Type: GrantFiled: April 25, 2002Date of Patent: October 17, 2006Assignee: Macronix International Co., Ltd.Inventors: Chen-Jung Tsai, Jui-Chung Lee, Chih-Wen Lin
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Patent number: 7105869Abstract: A multi-chip package is provided. A first die pad has a first chip attaching surface and a first unoccupied surface. A second die pad has a second chip attaching surface and a second unoccupied surface. The connecting structures are used for connecting the first die pad and the second die pad. The inner leads has wire connecting surfaces. The wire connecting surfaces, the first chip attaching surface and the second unoccupied surface face the same direction. A first chip has a first active surface and a first inactive surface. The first inactive surface is attached to the first chip attaching surface. A second chip has a second active surface and a second inactive surface. Part of the second active surface is attached to the second chip attaching surface. The wires are used for electrically connecting the first active surface and the second active surface to the wire connecting surfaces.Type: GrantFiled: October 29, 2004Date of Patent: September 12, 2006Assignee: Macronix International Co., Ltd.Inventors: Jui-Chung Lee, Ji-Gang Lee, Jing-Ming Chiu
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Publication number: 20060097282Abstract: A multi-chip package is provided. A first die pad has a first chip attaching surface and a first unoccupied surface. A second die pad has a second chip attaching surface and a second unoccupied surface. The connecting structures are used for connecting the first die pad and the second die pad. The inner leads has wire connecting surfaces. The wire connecting surfaces, the first chip attaching surface and the second unoccupied surface face the same direction. A first chip has a first active surface and a first inactive surface. The first inactive surface is attached to the first chip attaching surface. A second chip has a second active surface and a second inactive surface. Part of the second active surface is attached to the second chip attaching surface. The wires are used for electrically connecting the first active surface and the second active surface to the wire connecting surfaces.Type: ApplicationFiled: October 29, 2004Publication date: May 11, 2006Inventors: Jui-Chung Lee, Ji-Gang Lee, Jing-Ming Chiu
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Patent number: 6977436Abstract: A semiconductor packaging device has a carrier having at least a portion configured for containing a chip. The chip, affixing to the portion with sidewall, has a back surface an active surface, which multitudes of bonding pads are on the active surface. One insulating layer on the active surface and carrier has multitudes of conductive holes corresponding to the first bonding pads. A multi-layer structure on the insulating layer is configured for providing electrical connection to the conductive holes. Another insulating layer, affixed on one of the carrier and the multi-layer structure, has another conductive holes electrically connected to the conductive holes. Multitudes of solder balls, on at least one of the carrier and latter insulating layer, electrically connect the latter conductive holes.Type: GrantFiled: February 14, 2002Date of Patent: December 20, 2005Assignee: Macronix International Co. Ltd.Inventors: Chen-Jung Tsai, Jui-Chung Lee, Chih-Wen Lin
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Publication number: 20040021230Abstract: A stacking multi-chip device comprises a substrate having a recess, stud bumpers or conductive stud strips thereon. A low die has a back surface affixed in the recess or the substrate, and has a first active surface comprising a plurality of bonding pads. The bonding pads of the low die have a set of elongate conductors connected to the substrate. An upper die has a back surface and a second active surface comprising a plurality of bonding pads. The bonding pads of the upper die have a plurality of stud bumpers connected to the stud bumpers, conductive stud strips, or the substrate by the method of reflow or anti-tropic conductive film. The second active surface is faced towards said first active surface and is offset stacked atop the low die to expose all bonding pads.Type: ApplicationFiled: August 5, 2002Publication date: February 5, 2004Applicant: Macronix International Co., Ltd.Inventors: Chen-Jung Tsai, Jui-Chung Lee, Chih-Wen Lin
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Publication number: 20040000703Abstract: A semiconductor package body having a lead frame. The lead frame is electrically connected to a semiconductor chip via at least one bonding wire in the semiconductor package body. The lead frame has a die pedestal having a first surface and a second surface opposite each other, a base pad disposed outside the die pedestal, at least one connecting part providing a connection between the die pedestal and the base pad, and a plurality of leads. Each lead has an electrical connecting portion and a connecting foot portion, in which the electrical connecting portion is electrically connected to the semiconductor chip via the bonding wire, and the connecting foot portion is exposed to the exterior of the semiconductor package body, thereby providing enhanced heat dissipation.Type: ApplicationFiled: December 26, 2002Publication date: January 1, 2004Inventors: Jui-chung Lee, Chen-Jung Tsai, Chih-Wen Lin
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Patent number: 6650008Abstract: A stacked semiconductor packaging device consists of at least a stacked multi-chip device comprising a substrate. A first chip has a back surface faced towards the substrate and an active surface comprising a plurality of bonding pads which have a first set of elongate conductors connected to the substrate. A second chip has another back surface and another active surface comprising a plurality of bonding pads which have a second set of elongate conductors connected to the substrate. The active surface of the second chip is faced towards the active surface of said first chip and is stacked atop the first chip so as to expose all of the bonding pads. The face-to-face arrangement of the first chip and the second chip can reduce the whole packing height.Type: GrantFiled: March 26, 2002Date of Patent: November 18, 2003Assignee: Macronix International Co., Ltd.Inventors: Chen-Jung Tsai, Jui-Chung Lee, Chih-Wen Lin