SEMICONDUCTOR PACKAGING DEVICE AND MANUFACTURE THEREOF
A semiconductor packaging device comprises a carrier having at least a cavity/a slot thereon, at least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second plating through holes therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads.
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This application is a continuation application of U.S. application Ser. No. 10/131,485 filed Apr. 25, 2002, the disclosure of which is hereby incorporated by reference herein in its entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to a stacking semiconductor packaging device and manufacture thereof, and more particularly relates to a structure of flip chip ball grid array (FCBGA) and manufacture thereof.
2. Description of the Prior Art
In packaging manufacture, especially in packaging manufacture of FCBGA for integrated circuits (ICs) of high-density I/O or few I/O on small area, the bonding pads on ICs need to be rearranged for an array by a redistribution process, followed by the formation of under-bumping-metallization layer and solder bumps. Due to the limitation of general print circuit board (PCB) on the high-density I/O layout of integrated circuits, a flip chip is first affixed to a build-up substrate, followed by fanning-out the I/O pins of the flip chip to become great-pitch-distribution area.
However, due to the small solder bumps on the flip chips and the difference of thermal expansion between the solder bumps and the BT substrate, it is necessary to fill the gaps among the flip chip, solder bumps, and a general substrate with underfilled gel on consideration of reliability. Thus, the consumptions of time and cost for such a process are high.
SUMMARY OF THE INVENTIONIt is one object of the present invention to provide a semiconductor packaging and manufacture thereof. An additionally high-cost fan-out process and thereto relative steps are not necessary for the present invention.
Improved structure of FCBGA and manufacture thereof. The redistribution and solder-bump process for a conventional structure of FCBGA are simplified and integrated into the fan-out process of build-up substrate.
It is further object of the present invention to provide a novel packaging structure with improved reliability and manufacture thereof. A chip is prevented from affixing to a PCB directly such that a thickness of the novel packing structure is minimum and met with the requirement of heat radiation.
In the present invention, a semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second plating through holes therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls. Such architecture integrates the redistribution and fan-out process, which simplifies the conventional process for flip-chip ball grid array.
BRIEF DESCRIPTION OF THE DRAWINGSA better understanding of the invention may be derived by reading the following detailed description with reference to the accompanying drawings wherein:
While the invention is described in terms of a single preferred embodiment, those skilled in the art will recognize that many devices described below can be altered as well as other substitutions with same function and can be freely made without departing from the spirit and scope of the invention.
Furthermore, there is shown a representative portion of semiconductor packaging of the present invention in enlarged. The drawings are not necessarily to scale for clarify of illustration and should not be interpreted in a limiting sense. Furthermore, the present invention can be applied on various multichip devices or packages.
In the present invention, a semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second plating through holes therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls. Such architecture integrates the redistribution and fan-out process, which simplifies the conventional process for flip-chip ball grid array.
A layout for second conductive via holes and a multi-layer circuit are implemented on the insulating layer (step 54). The multi-layer circuit connects electrically the first via holes with the second via holes. Next, the re-distribution is implemented (step 55), wherein those re-distributed bonding pads are located corresponding to the second conductive via holes and aligned to a great-pitch array on a substrate. It can be implemented by conventional redistribution process and the process of under bump metallization. That is, a single/multi-layer film with predetermined circuit and plating through holes is used to adhered to the adhesive on the chips and the carrier, wherein the plating through holes are connected to the bonding pads of the chip. Then another adhesive is coated on the single/multi-layer film and the pads of the plating through holes are exposed. Furthermore, one or more chips similar or different in sizes are stacked on the above-mentioned structure by the flip-chip technology (step 56). Next, the packaging chips are grinded and sawed followed by attaching multitudes of solder balls to the predetermined location (the locations of re-distributed pads and the second via holes) and reflow (step 57). The attachment of the solder balls can be implemented by conventional methods for ball grid array. Furthermore, the chips and the carriers can be grinded to a predetermined packaging thickness.
Next, one or more chips are stacked by the flip-chip technology and affixed through the bonding pads 41 of the chips 40, solder balls 42, and the flip-chip pads 43. Then the solder balls 17 are affixed to the pads 18 of the plating through holes. To be specific, the chips 40 would have the sizes similar to or different from the chip 20 has. Furthermore, it is necessary for the solder balls 17 to have a vertical height thicker than the height summation of the chips 40, bonding pads 41, and the solder balls 43, and so on. Thus, the pad redistribution, bumping, and fan-out processes for the chips can be implemented at one time. One of advantages of the present invention is to avoid the direct chip attachment to a print circuit board for fear of poor reliability. Furthermore, the packaging thickness is minimum and the heat radiation is improved. On the other hand, it is not necessary to polish the chips so thin to meet the limitation of the stacked height. Furthermore, it is not necessary for the present invention to have any space for associating the wire-bonding process, such that the stacked height is further reduced.
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Depicted
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
Claims
1. An interface for chip assembly comprising,
- a first insulating layer comprising a plurality of first connectors for connecting to a first chip;
- a second insulating layer comprising a plurality of second connectors for connecting to a second chip and a plurality of third connectors for connecting to a circuit board; and
- a third insulating layer between said first and second insulating layers, comprising a plurality of conductive layout lines for arranging the connection between said first, second, and third connectors.
2. An interface for chip assembly as claimed in claim 1, wherein said first insulating layer is affixed to a carrier which comprises said first chip.
3. An interface for chip assembly as claimed in claim 1, wherein said plurality of first connectors are connecting to said first chip via bonding pads.
4. An interface for chip assembly as claimed in claim 1, wherein said plurality of second connectors are connecting to said second chip via a ball grid array.
5. An interface for chip assembly as claimed in claim 1, wherein said plurality of third connectors are connecting to said circuit board via a ball grid array.
6. An interface for chip assembly as claimed in claim 5, wherein height of said ball grid array is higher than said second chip.
Type: Application
Filed: Sep 7, 2006
Publication Date: Jan 25, 2007
Applicant: MACRONIX INTERNATIONAL CO., LTD. (HSIN-CHU CITY)
Inventors: Chen-Jung TSAI (HSIN-CHU), Jui-Chung LEE (YUN-LIN), Chih-Wen LIN (HSIN-CHU CITY)
Application Number: 11/470,870
International Classification: H01L 23/52 (20060101);