Patents by Inventor Julian Partridge
Julian Partridge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8208259Abstract: Cooling systems for computers are disclosed. In particular, embodiment of such cooling solutions may effectively be used in conjunction with mobile computers that have a polymer (or other type of) chassis. More specifically, embodiments of the present invention use micro vapor plates to conduct the heat generated by one or more electronic components of a mobile computer to the chassis of the mobile computer such that the heat from the electronic components is conducted into, and spread over, at least a portion of the surface of the chassis. The mobile computer can then be cooled by convection or radiation.Type: GrantFiled: May 7, 2010Date of Patent: June 26, 2012Assignee: Augmentix CorporationInventors: Mark Wolfe, Julian Partridge
-
Patent number: 7804985Abstract: Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.Type: GrantFiled: August 25, 2008Date of Patent: September 28, 2010Assignee: Entorian Technologies LPInventors: Leland Szewerenko, Julian Partridge, Ron Orris
-
Patent number: 7759791Abstract: A system and method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die to a substrate opposite a first die bonded to the substrate. The second die is bonded using heat conducted through the first die to the substrate, and optionally through an underfill material. The first and second die are connected such that bumps are connected to common bonding pads on the substrate. Bumps on one of the die extend through openings in the substrate to connect to the common bonding pads. The bonding pads are within the perimeter of the first die.Type: GrantFiled: April 20, 2007Date of Patent: July 20, 2010Assignee: Entorian Technologies LPInventors: Julian Partridge, Leland Szewerenko, James Douglas Wehrly, Jr.
-
Patent number: 7760513Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. The populated flexible circuitry is disposed proximal to a rigid substrate to place the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The rigid substrate exhibits adhesion features that allow more advantageous use of thermoplastic adhesives with concomitant rework advantages and while providing flexibility in meeting dimensional specifications such as those promulgated by JEDEC, for example.Type: GrantFiled: April 3, 2006Date of Patent: July 20, 2010Assignee: Entorian Technologies LPInventors: Julian Partridge, David Roper, Paul Goodwin
-
Patent number: 7675155Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.Type: GrantFiled: October 31, 2008Date of Patent: March 9, 2010Assignee: Entorian Technologies, LPInventor: Julian Partridge
-
Patent number: 7656678Abstract: The present invention stacks integrated circuit packages into circuit modules. In a preferred embodiment, solder paste and primary adhesive respectively are applied to selected locations on the flex circuitry. Supplemental adhesive is applied to additional locations on the flex circuitry, CSP, or other component. The flex circuitry and the CSP are brought into proximity with each other. During solder reflow operation, a force is applied and the CSP collapses toward the flex circuitry, displacing the primary adhesive and the supplemental adhesive. The supplemental adhesive establishes a bond providing additional support to the flex circuitry. In another embodiment, CSPs or other integrated circuit packages are bonded to each other or to other components with a combination of adhesives. A rapid bond adhesive maintains alignment of the bonded packages and/or components during assembly, and a structural bond adhesive provides additional strength and/or structural integrity to the bond.Type: GrantFiled: October 31, 2005Date of Patent: February 2, 2010Assignee: Entorian Technologies, LPInventors: Julian Partridge, James Douglas Wehrly, Jr., David L. Roper, Joseph Villani
-
Publication number: 20090309214Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.Type: ApplicationFiled: August 24, 2009Publication date: December 17, 2009Inventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman, Paul Goodwin
-
Publication number: 20090298230Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.Type: ApplicationFiled: August 10, 2009Publication date: December 3, 2009Inventors: Julian Partridge, James Douglas Wehrly, JR.
-
Publication number: 20090294948Abstract: The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.Type: ApplicationFiled: August 10, 2009Publication date: December 3, 2009Inventors: Julian Partridge, Roel Perez, Leland Szewerenko
-
Patent number: 7626273Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.Type: GrantFiled: January 20, 2009Date of Patent: December 1, 2009Assignee: Entorian Technologies, L.P.Inventors: Julian Partridge, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr.
-
Publication number: 20090273069Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers.Type: ApplicationFiled: May 7, 2009Publication date: November 5, 2009Inventors: James W. Cady, Julian Partridge, James Douglas Wehrly, JR., James Wilder
-
Patent number: 7579687Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.Type: GrantFiled: January 13, 2006Date of Patent: August 25, 2009Assignee: Entorian Technologies, LPInventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman, Paul Goodwin
-
Patent number: 7572671Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.Type: GrantFiled: October 4, 2007Date of Patent: August 11, 2009Assignee: Entorian Technologies, LPInventors: Julian Partridge, James Douglas Wehrly, Jr.
-
Patent number: 7573129Abstract: The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.Type: GrantFiled: September 20, 2006Date of Patent: August 11, 2009Assignee: Entorian Technologies, LPInventors: Julian Partridge, Roel Perez, Leland Szewerenko
-
Publication number: 20090124045Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.Type: ApplicationFiled: January 20, 2009Publication date: May 14, 2009Inventors: Julian Partridge, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, JR.
-
Patent number: 7508069Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.Type: GrantFiled: May 18, 2006Date of Patent: March 24, 2009Assignee: Entorian Technologies, LPInventors: James Douglas Wehrly, Jr., Ron Orris, Leland Szewerenko, Tim Roy, Julian Partridge, David L. Roper
-
Publication number: 20090072376Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.Type: ApplicationFiled: October 31, 2008Publication date: March 19, 2009Applicant: Entorian Technologies, LPInventor: Julian Partridge
-
Publication number: 20080308924Abstract: Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.Type: ApplicationFiled: August 25, 2008Publication date: December 18, 2008Inventors: Leland Szewerenko, Julian Partridge, Ron Orris
-
Patent number: 7446403Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.Type: GrantFiled: June 14, 2006Date of Patent: November 4, 2008Assignee: Entorian Technologies, LPInventor: Julian Partridge
-
Publication number: 20080211077Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers.Type: ApplicationFiled: May 11, 2006Publication date: September 4, 2008Inventors: James W. Cady, Julian Partridge, James Douglas Wehrly, James Wilder, David L. Roper, Jeffrey Alan Buchle