Patents by Inventor Julian Partridge

Julian Partridge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7417310
    Abstract: Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: August 26, 2008
    Assignee: Entorian Technologies, LP
    Inventors: Leland Szewerenko, Julian Partridge, Ron Orris
  • Publication number: 20080122054
    Abstract: Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 29, 2008
    Inventors: Leland Szewerenko, Julian Partridge, Ron Orris
  • Patent number: 7375418
    Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while traces that implement stacking-related intra-stack connections between the constituent ICs are implemented in interposers or carrier structures oriented along the leaded sides of the stack and which extend beyond the perimeter of the feet of the leads of the constituent ICs or beyond the connective pads of the interposer. This leaves open to air flow, most of the transit section of the lower lead for cooling, but provides a less complex board structure for implementation of intra-stack connections.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: May 20, 2008
    Assignee: Entorian Technologies, LP
    Inventor: Julian Partridge
  • Patent number: 7371609
    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: May 13, 2008
    Assignee: Staktek Group L.P.
    Inventors: Julian Partridge, James Douglas Wehrly, Jr.
  • Publication number: 20080093734
    Abstract: A system a method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die to a substrate opposite a first die bonded to the substrate. The second die is bonded using heat conducted through the first die to the substrate, and optionally through an underfill material. The first and second die are connected such that bumps are connected to common bonding pads on the substrate. Bumps on one of the die extend through openings in the substrate to connect to the common bonding pads. The bonding pads are within the perimeter of the first die.
    Type: Application
    Filed: April 20, 2007
    Publication date: April 24, 2008
    Applicant: STAKTEK GROUP L.P.
    Inventors: Julian Partridge, Leland Szewerenko, James Douglas Wehrly
  • Publication number: 20080036068
    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.
    Type: Application
    Filed: October 4, 2007
    Publication date: February 14, 2008
    Inventors: Julian Partridge, James Wehrly
  • Patent number: 7323364
    Abstract: A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: January 29, 2008
    Assignee: Staktek Group L.P.
    Inventors: Julian Partridge, James Douglas Wehrly, Jr., David Roper
  • Publication number: 20070290314
    Abstract: The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.
    Type: Application
    Filed: September 20, 2006
    Publication date: December 20, 2007
    Inventors: Julian Partridge, Roel Perez, Leland Szewerenko
  • Publication number: 20070290312
    Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.
    Type: Application
    Filed: June 14, 2006
    Publication date: December 20, 2007
    Inventor: Julian Partridge
  • Publication number: 20070290313
    Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while traces that implement stacking-related intra-stack connections between the constituent ICs are implemented in interposers or carrier structures oriented along the leaded sides of the stack and which extend beyond the perimeter of the feet of the leads of the constituent ICs or beyond the connective pads of the interposer. This leaves open to air flow, most of the transit section of the lower lead for cooling, but provides a less complex board structure for implementation of intra-stack connections.
    Type: Application
    Filed: June 14, 2006
    Publication date: December 20, 2007
    Inventor: Julian Partridge
  • Patent number: 7304382
    Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: December 4, 2007
    Assignee: Staktek Group L.P.
    Inventors: James Douglas Wehrly, Jr., Ron Orris, Leland Szewerenko, Tim Roy, Julian Partridge, David L. Roper
  • Publication number: 20070159545
    Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.
    Type: Application
    Filed: May 18, 2006
    Publication date: July 12, 2007
    Inventors: James Wehrly, Ron Orris, Leland Szewerenko, Tim Roy, Julian Partridge, David Roper
  • Publication number: 20070158800
    Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.
    Type: Application
    Filed: May 18, 2006
    Publication date: July 12, 2007
    Inventors: James Wehrly, Ron Orris, Leland Szewerenko, Tim Roy, Julian Partridge, David Roper
  • Publication number: 20070117262
    Abstract: The present invention provides a system and method that amounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
    Type: Application
    Filed: January 23, 2007
    Publication date: May 24, 2007
    Inventors: Julian Partridge, James Cady, James Wilder, David Roper, James Wehrly
  • Publication number: 20070114649
    Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method is stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder past that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
    Type: Application
    Filed: January 23, 2007
    Publication date: May 24, 2007
    Inventors: Julian Partridge, James Cady, James Wilder, David Roper, James Wehrly
  • Patent number: 7180167
    Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: February 20, 2007
    Assignee: Staktek Group L. P.
    Inventors: Julian Partridge, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr.
  • Publication number: 20060263938
    Abstract: A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.
    Type: Application
    Filed: April 25, 2006
    Publication date: November 23, 2006
    Inventors: Julian Partridge, James Wehrly, David Roper
  • Publication number: 20060198238
    Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. The populated flexible circuitry is disposed proximal to a rigid substrate to place the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The rigid substrate exhibits adhesion features that allow more advantageous use of thermoplastic adhesives with concomitant rework advantages and while providing flexibility in meeting dimensional specifications such as those promulgated by JEDEC, for example.
    Type: Application
    Filed: April 3, 2006
    Publication date: September 7, 2006
    Inventors: Julian Partridge, David Roper, Paul Goodwin
  • Patent number: 7094632
    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: August 22, 2006
    Assignee: Staktek Group L.P.
    Inventors: James W. Cady, Julian Partridge, James Douglas Wehrly, Jr., James Wilder, David L. Roper, Jeff Buchle
  • Publication number: 20060129888
    Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.
    Type: Application
    Filed: January 13, 2006
    Publication date: June 15, 2006
    Inventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman`, Paul Goodwin